Inventor
BRADFIELD TRAVIS ALISTER
US3 patents
Patents
3 patentsUS6922817B2Jul 26, 2005
System and method for achieving timing closure in fixed placed designs after implementing logic changes
LSI LOGIC CORP32 citations85
US6886147B2Apr 26, 2005
Method, system, and product for achieving optimal timing in a data path that includes variable delay lines and coupled endpoints
LSI LOGIC CORP9 citations68
US7107375B2Sep 12, 2006
Method for improving selection performance by using an arbitration elimination scheme in a SCSI topology
LSI LOGIC CORP3 citations60