Inventor

KUNG CHEE-WEI

MY2 patents

Patents

2 patents

US9024657B2May 5, 2015

Architectural floorplan for a structured ASIC manufactured on a 28 NM CMOS process lithographic node or smaller

EASIC CORP9 citations75

US8957398B2Feb 17, 2015

Via-configurable high-performance logic block involving transistor chains

EASIC CORP4 citations68