Inventor

SHAHIDI GHAVAM

US34 patents

⚠️ This page may combine multiple inventors who share the name “SHAHIDI GHAVAM”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SHAHIDI GHAVAM

IBM

Ion implantation combined with in situ or ex situ heat treatment for improved field effect transistors

Process of fabricating planar and densely patterned silicon-on-insulator structure

Strained silicon-on-insulator by anodization of a buried p+ silicon germanium layer

Method to form Si-containing SOI and underlying substrate with different orientations

Thin film transistors with epitaxial source/drain contact regions

Buried channel MOSFET using III-V compound semiconductors and high k gate dielectrics

Strained semiconductor-on-insulator (sSOI) by a simox method

Disposable metallic or semiconductor gate spacer

Heterojunction III-V photovoltaic cell fabrication

Strained semiconductor-on-insulator (sSOI) by a simox method

Planar and densely patterned silicon-on-insulator structure

CMOS-compatible high-speed and low-power random number generator

Formation of fully silicided (FUSI) gate using a dual silicide process

Autonomous integrated circuits

Method and structure for forming on-chip high quality capacitors with ETSOI transistors

Method to form Si-containing SOI and underlying substrate with different orientations

Strained silicon-on-insulator by anodization of a buried p+ silicon germanium layer

System implementation of one-time programmable memories

Ultrathin SOI CMOS devices employing differential STI liners

Fully silicided metal gate semiconductor device structure

Thin film transistors with epitaxial source/drain contact regions

Low-power random number generator

Ultrathin SOI CMOS devices employing differential STI liners

CHENG KANGGUO

Raised source/drain structure for enhanced strain coupling from stress liner

Method of forming extremely thin semiconductor on insulator (ETSOI) device without ion implantation

Raised source/drain structure for enhanced strain coupling from stress liner

Method and structure for forming on-chip high quality capacitors with ETSOI transistors

Forming narrow fins for finFET devices using asymmetrically spaced mandrels

Fully-depleted SON

Raised source/drain structure for enhanced strain coupling from stress liner

CHANG LELAND

Contact scheme for FINFET structures with multiple FINs

KULKARNI PRANITA

FinFET device having reduce capacitance, access resistance, and contact resistance

ELPIS TECH INC

Thin film interconnects with large grains

BEDELL STEPHEN W

Heterojunction III-V photovoltaic cell fabrication