Inventor

PODDAR ANINDYA

US66 patents

⚠️ This page may combine multiple inventors who share the name “PODDAR ANINDYA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PODDAR ANINDYA

TEXAS INSTRUMENTS INC

Multilayer high voltage isolation barrier in an integrated circuit

Open cavity package using chip-embedding technology

Printed repassivation for wafer chip scale packaging

Metal ribs in electromechanical devices

Copper passivation

Semiconductor systems having premolded dual leadframes

Integration of a passive component in a cavity of an integrated circuit package

Bump bond structure for enhanced electromigration performance

Packages with electrical fuses

Semiconductor device package with thermal pad

Forming integrated inductors and transformers with embedded magnetic cores

High voltage flip-chip on lead (FOL) package

Conductive members atop semiconductor packages

Metal ribs in electromechanical devices

Embedded die packaging with integrated ceramic substrate

Semiconductor package having an interdigitated mold arrangement

Semiconductor package with isolated heat spreader

Packaged semiconductor devices for high voltage with die edge protection

Integrated circuit backside metallization

Semiconductor package with isolated heat spreader

Embedded die packaging with integrated ceramic substrate

Integrated circuit backside metallization

Packaged semiconductor devices for high voltage with die edge protection

High voltage flip-chip on lead (FOL) package

Stress buffer layer in embedded package

Embedded die package multichip module

NAT SEMICONDUCTOR CORP

Stacked die package for semiconductor devices

Process and structure improvements to shellcase style packaging technology

Method and apparatus for lead-frame based grid array IC packaging

Integrated circuit package

Spacer with passive components for use in multi-chip modules

Wafer level optoelectronic package with fiber side insertion

Thermal release wafer mount tape with B-stage adhesive

Thermal release wafer mount tape with B-stage adhesive

Integrated circuit package having offset segmentation of package power and/or ground planes and methods for reducing delamination in integrated circuit packages

Substrate strips for use in integrated circuit packaging

Intergrated circuit packaging with improved die bonding

Bond pad stacks for ESD under pad and active under pad bonding

Methods and systems for packaging integrated circuits with integrated passive components

Integrated circuit package having die with staggered bond pads and die pad assignment methodology for assembly of staggered die in single-tier ebga packages

Inkjet printed leadframe

Gang flipping for IC packaging

Under-bond pad structures for integrated circuit devices

Integrated circuit package having offset die

Integrated circuit package

Method of packaging integrated circuits

PODDAR ANINDYA

Thermally efficient integrated circuit package

Method and apparatus for achieving galvanic isolation in package having integral isolation medium

Foil based semiconductor package

Micro surface mount device packaging