Inventor
MORROW MICHAEL W
US27 patents
⚠️ This page may combine multiple inventors who share the name “MORROW MICHAEL W”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
12 patentsUS6624535B2Sep 23, 2003
Digitally controlling the output voltage of a plurality of voltage sources
INTEL CORP78 citations98
US7120714B2Oct 10, 2006
High-speed starvation-free arbiter system, rotating-priority arbiter, and two stage arbitration method
INTEL CORP75 citations95
US7284137B2Oct 16, 2007
System and method for managing power consumption within an integrated circuit
INTEL CORP50 citations92
US6664775B1Dec 16, 2003
Apparatus having adjustable operational modes and method therefore
INTEL CORP37 citations89
US7596683B2Sep 29, 2009
Switching processor threads during long latencies
INTEL CORP8 citations84
US6898718B2May 24, 2005
Method and apparatus to monitor performance of a process
INTEL CORP18 citations84
US6949918B2Sep 27, 2005
Apparatus having adjustable operational modes and method therefore
INTEL CORP14 citations81
US7472390B2Dec 30, 2008
Method and apparatus to enable execution of a thread in a multi-threaded computer system
INTEL CORP4 citations63
US7415577B2Aug 19, 2008
Method and apparatus to write back data
INTEL CORP2 citations63
US7039763B2May 2, 2006
Apparatus and method to share a cache memory
INTEL CORP4 citations63
US7240168B2Jul 3, 2007
Method and system to order memory operations
INTEL CORP0 citations52
US7328313B2Feb 5, 2008
Methods to perform cache coherency in multiprocessor system using reserve signals and control bits
INTEL CORP0 citations42
MARVELL INT LTD
7 patentsUS7428645B2Sep 23, 2008
Methods and apparatus to selectively power functional units
MARVELL INT LTD18 citations92
US7437512B2Oct 14, 2008
Low power semi-trace instruction/trace hybrid cache with logic for indexing the trace cache under certain conditions
MARVELL INT LTD5 citations74
US7434027B2Oct 7, 2008
Translation lookaside buffer prediction mechanism
MARVELL INT LTD4 citations71
US9146607B1Sep 29, 2015
Methods and apparatus to selectively power functional units
MARVELL INT LTD1 citations63
US7822925B2Oct 26, 2010
Low power semi-trace instruction/trace hybrid cache with logic for indexing the trace cache under certain conditions
MARVELL INT LTD2 citations63
US7987337B1Jul 26, 2011
Translation lookaside buffer prediction mechanism
MARVELL INT LTD1 citations60
US7162609B2Jan 9, 2007
Translation lookaside buffer prediction mechanism
MARVELL INT LTD3 citations60
O'CONNOR DENNIS M
4 patentsUS8533395B2Sep 10, 2013
Moveable locked lines in a multi-level cache
O'CONNOR DENNIS M22 citations92
US8732490B1May 20, 2014
Methods and apparatus to selectively power functional units
O'CONNOR DENNIS M1 citations63
US8112643B2Feb 7, 2012
Methods and apparatus to selectively power functional units
O'CONNOR DENNIS M2 citations63
US7581065B2Aug 25, 2009
Low locality-of-reference support in a multi-level cache hierachy
O'CONNOR DENNIS M1 citations52