P

Inventor

LIN CHIH-SHENG

TW36 patents
⚠️ This page may combine multiple inventors who share the name “LIN CHIH-SHENG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

IND TECH RES INST

18 patents
US9136843B2Sep 15, 2015

Through silicon via repair circuit of semiconductor device

IND TECH RES INST4 citations73
US11599600B2Mar 7, 2023

Computing in memory cell

IND TECH RES INST2 citations71
US11423983B2Aug 23, 2022

Memory device and data weight state determining method for in-memory computation

IND TECH RES INST2 citations71
US7738289B2Jun 15, 2010

Memory accessing circuit and method

IND TECH RES INST2 citations62
US12260321B2Mar 25, 2025

Data feature augmentation system and method for low-precision neural network

IND TECH RES INST0 citations61
US11145356B2Oct 12, 2021

Computation operator in memory and operation method thereof

IND TECH RES INST1 citations61
US10914618B2Feb 9, 2021

Readout circuit for sensor and readout method thereof

IND TECH RES INST0 citations61
US7486546B2Feb 3, 2009

Multi-state sense amplifier

IND TECH RES INST4 citations61
US7385866B2Jun 10, 2008

Load-balanced apparatus of memory

IND TECH RES INST6 citations61
US11741189B2Aug 29, 2023

Computing in memory cell

IND TECH RES INST0 citations60
US9368271B2Jun 14, 2016

Three-dimension symmetrical vertical transformer

IND TECH RES INST1 citations51
US12406721B2Sep 2, 2025

Memory cell

IND TECH RES INST0 citations50
US12142342B2Nov 12, 2024

Memory circuit with sense amplifier calibration mechanism

IND TECH RES INST0 citations50
US10324054B2Jun 18, 2019

Method of manufacturing sensor device

IND TECH RES INST0 citations50
US10156535B2Dec 18, 2018

Sensor device and method of manufacturing the same

IND TECH RES INST0 citations50
US10101175B2Oct 16, 2018

Sensor interface circuit and sensor output adjusting method

IND TECH RES INST0 citations50
US9076771B2Jul 7, 2015

Varactor that applies bias voltage to two through wafer vias to determine capacitance of depletion region capacitor formed between the two through wafer vias

IND TECH RES INST1 citations50
US7894274B2Feb 22, 2011

Memories with improved write current

IND TECH RES INST0 citations40

TAIWAN SEMICONDUCTOR MFG

3 patents

LIN CHIH-SHENG

3 patents

SU KENG-LI

3 patents

FULIAN YUZHAN PRECISION TECH CO LTD

2 patents

SONG KAI-TAI

1 patent

UNIV NATIONAL CHIAO TUNG

1 patent

(unassigned)

1 patent

CHEN SZ-HAU

1 patent

LAI HSIN-CHI

1 patent

TAIN RA-MIN

1 patent

SILICONWARE PRECISION INDUSTRIES CO LTD

1 patent