P

Inventor

O'NEILL ARTHUR J

US26 patents
⚠️ This page may combine multiple inventors who share the name “O'NEILL ARTHUR J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

IBM

17 patents
US7502986B2Mar 10, 2009

Method and apparatus for collecting failure information on error correction code (ECC) protected data

IBM15 citations92
US9244851B2Jan 26, 2016

Cache coherency protocol for allowing parallel data fetches and eviction to the same addressable index

IBM6 citations84
US9065481B2Jun 23, 2015

Bad wordline/array detection in memory

IBM8 citations84
US8423875B2Apr 16, 2013

Collecting failure information on error correction code (ECC) protected data

IBM6 citations84
US9348524B1May 24, 2016

Memory controlled operations under dynamic relocation of storage

IBM3 citations73
US8996819B2Mar 31, 2015

Performance optimization and dynamic resource reservation for guaranteed coherency updates in a multi-level cache hierarchy

IBM4 citations72
US9047199B2Jun 2, 2015

Reducing penalties for cache accessing operations

IBM2 citations60
US9086990B2Jul 21, 2015

Bitline deletion

IBM0 citations52
US10824565B2Nov 3, 2020

Configuration based cache coherency protocol selection

IBM0 citations51
US10402328B2Sep 3, 2019

Configuration based cache coherency protocol selection

IBM0 citations51
US10394712B2Aug 27, 2019

Configuration based cache coherency protocol selection

IBM0 citations51
US9792213B2Oct 17, 2017

Mitigating busy time in a high performance cache

IBM0 citations51
US9158694B2Oct 13, 2015

Mitigating busy time in a high performance cache

IBM0 citations51
US7685345B2Mar 23, 2010

Apparatus and method for fairness arbitration for a shared pipeline in a large SMP computer system

IBM3 citations51
US9037806B2May 19, 2015

Reducing store operation busy times

IBM0 citations50
US9298468B2Mar 29, 2016

Monitoring processing time in a shared pipeline

IBM0 citations49
US8001328B2Aug 16, 2011

Method and process for expediting the return of line exclusivity to a given processor through enhanced inter-node communications

IBM0 citations49

AMBROLADZE EKATERINA M

2 patents

BERGER DEANNA P

2 patents

MEANEY PATRICK J

1 patent

O'NEILL ARTHUR J

1 patent

BERGER DEANNA POSTLES DUNN

1 patent

FEE MICHAEL F

1 patent

BLAKE MICHAEL A

1 patent