Inventor

HORNE STEPHEN C

US47 patents

⚠️ This page may combine multiple inventors who share the name “HORNE STEPHEN C”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HORNE STEPHEN C

ADVANCED MICRO DEVICES INC

Compact, dual-transistor integrated circuit

Circuit configuration employing a compare unit for testing variably controlled delay units

Self-adjusting variable drive strength buffer circuit and method for controlling the drive strength of a buffer circuit

Configuration and method for testing a delay chain within a microprocessor clock generator

Forming local interconnects in integrated circuits

Memory device using a reduced word line voltage during read operations and a method of accessing such a memory device

Microprocessor with distributed clock generators

Interlock acquisition for critical code section execution in a shared memory common-bus individually cached multiprocessor system

Digital clock waveform generator and method for generating a clock signal

Processing system and method including lock buffer for controlling exclusive critical problem accesses by each processor

Minimizing transistor size in integrated circuits

Method for self-aligning polysilicon gates with field isolation and the resultant structure

Distributed gated clock driver

Memory cell having increased capacitance via a local interconnect to gate capacitor and a method for making such a cell

Data cache and method for handling memory errors during copy-back

Forming minimal size spaces in integrated circuit conductive lines

Variable strength clock signal driver and method of manufacturing the same

Minimizing transistor size in integrated circuits

Minimizing transistor size in integrated circuits

Variable strength clock signal driver and method of manufacturing the same

INTRINSITY INC

Method and apparatus for generating clock signals

Method and apparatus for a RAM circuit having N-Nary output interface

Method and apparatus for logic synchronization

Method and apparatus for a logic circuit with constant power consumption

Dynamic logic scan gate method and apparatus

Method and apparatus for a 1 of N signal

Dynamic logic scan gate method and apparatus

Method and apparatus for logic synchronization

Method and apparatus for an N-NARY logic circuit

Method and apparatus that allows the logic state of a logic gate to be tested when stopping or starting the logic gate&#39;s clock

Method and apparatus for 1 of 4 register file design

Generation of route rules

Method and apparatus for scan of synchronized dynamic logic using embedded scan gates

Method and apparatus for a N-nary logic circuit using capacitance isolation

Method and apparatus for a N-NARY logic circuit using capacitance isolation

Method and apparatus for a special stress mode for N-NARY logic that initializes the logic into a functionally illegal state

Method for calculating dynamic logic block propagation delay targets using time borrowing

EVSX INC

Method and apparatus for a N-nary logic circuit using 1 of N signals

Method and apparatus for a N-nary logic circuit using 1 of 4 signals

Method and apparatus for a RAM circuit having N-nary output interface

Method and apparatus for an address triggered RAM circuit

Method and apparatus for multi-bit register cell

Method and apparatus for a RAM circuit having N-nary word line generation

APPLE INC

Device input modes with corresponding cover configurations

Mechanism for protecting integrated circuits from security attacks

ADVANCED MICRODEVICES INC

Forming minimal size spaces in integrated circuit conductive lines

MCCOMBS EDWARD M

Memory including a reduced leakage wordline driver

Method and apparatus that allows the logic state of a logic gate to be tested when stopping or starting the logic gate's clock