Inventor

HERNER SCOTT BRAD

US124 patents

⚠️ This page may combine multiple inventors who share the name “HERNER SCOTT BRAD”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HERNER SCOTT BRAD

HERNER SCOTT BRAD

Interconnects for stacked non-volatile memory device and method

Vertical diodes for non-volatile memory device

Interconnects for stacked non-volatile memory device and method

Pillar structure for memory device and method

Method for obtaining smooth, continuous silver film

On/off ratio for non-volatile memory device and method

p+ polysilicon material on aluminum for non-volatile memory device and method

Disturb-resistant non-volatile memory device using via-fill and etchback technique

On/off ratio for non-volatile memory device and method

Method for obtaining smooth, continuous silver film

Disturb-resistant non-volatile memory device and method

Selective removal method and structure of silver in resistive switching device for a non-volatile memory device

Large array of upward pointinig p-i-n diodes having large and uniform current

Large array of upward pointing P-I-N diodes having large and uniform current

Pixel or display with sub pixels selected by antifuse programming

Package-less LED assembly and method

SUNRISE MEMORY CORP

3-dimensional NOR memory array with very fine pitch: device and method

Staggered word line architecture for reduced disturb in 3-dimensional NOR memory arrays

3-dimensional NOR memory array architecture and methods for fabrication thereof

Vertical thing-film transistor and application as bit-line connector for 3-dimensional memory arrays

3-dimensional NOR memory array architecture and methods for fabrication thereof

Staggered word line architecture for reduced disturb in 3-dimensional NOR memory arrays

Process for forming a vertical thin-film transistor that serves as a connector to a bit-line of a 3-dimensional memory array

Staggered word line architecture for reduced disturb in 3-dimensional NOR memory arrays

Methods for forming multilayer horizontal NOR-type thin-film memory strings

Methods for forming multi-layer vertical NOR-type memory string arrays

Method for in situ preparation of antimony-doped silicon and silicon germanium films

Wafer bonding in fabrication of 3-dimensional NOR memory circuits

3-dimensional NOR memory array architecture and methods for fabrication thereof

Fabrication method for a 3-dimensional NOR memory array

GLO AB

Nanowire LED structure and method for manufacturing the same

Nanowire sized opto-electronic structure and method for modifying selected portions of same

Nanowire sized opto-electronic structure and method for modifying selected portions of same

High index dielectric film to increase extraction efficiency of nanowire LEDs

Use of dielectric film to reduce resistivity of transparent conductive oxide in nanowire LEDs

Method of stress induced cleaving of semiconductor devices

LED submount with integrated interconnects

CROSSBAR INC

Disturb-resistant non-volatile memory device and method

Pillar structure for memory device and method

Disturb-resistant non-volatile memory device using via-fill and etchback technique

Interconnects for stacked non-volatile memory device and method

APPLIED MATERIALS INC

Wafer pretreatment to decrease rate of silicon dioxide deposition on silicon nitride compared to silicon substrate

Reduced fluorine contamination for tungsten CVD

Silicon layer to improve plug filling by CVD

SANDISK 3D LLC

Deposited semiconductor structure to minimize N-type dopant diffusion and method of making

Low resistivity titanium silicide on heavily doped semiconductor

Dielectric-based memory cells having multi-level one-time programmable and bi-level rewriteable operating modes and methods of forming the same

MATRIX SEMICONDUCTOR INC

Dummy wafers and methods for making the same

GEE HARRY

Three dimension programmable resistive random accessed memory array with shared bitline and method

CLARK MARK HAROLD

Seed layer for a p+ silicon germanium material for a non-volatile memory device and method