Inventor

ALAMELDEEN ALAA R

US36 patents

⚠️ This page may combine multiple inventors who share the name “ALAMELDEEN ALAA R”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ALAMELDEEN ALAA R

INTEL CORP

Selective error correction in memory to reduce power consumption

System and method for thread scheduling on reconfigurable processor cores

Multi-level memory management

Method and apparatus for implementing a heterogeneous memory subsystem

Method and apparatus for implementing a heterogeneous memory subsystem

Read-write partitioning of cache memory

Systems and methods for managing reconfigurable processor cores

Method and apparatus to efficiently track locations of dirty cache lines in a cache in a two-level main memory

Method, system, and device for near-memory processing with cores of a plurality of sizes

Providing dead-block prediction for determining whether to cache data in cache devices

Processor instructions for data compression and decompression

Cache architecture using way ID to reduce near memory traffic in a two-level memory system

Techniques for decoupled access-execute near-memory processing

Techniques for decoupled access-execute near-memory processing

Virtual machine replication and migration

Direct mapped caching scheme for a memory side cache that exhibits associativity in response to blocking from pinning

Multi-level memory management

Data compression in processor caches

Method and apparatus for pre-fetching data in a system having a multi-level system memory

Multi-level system memory with near memory capable of storing compressed cache lines

Replacement of a block with a compressed block to increase capacity of a memory-side cache

Two-level main memory hierarchy management

Adaptive granularity for reducing cache coherence overhead

Method and apparatus for multi-level memory early page demotion

Near memory miss prediction to reduce memory access latency

Method and apparatus for unneeded block prediction in a computing system having a last level cache and a multi-level system memory

Apparatus, system, and method to determine a demarcation voltage to use to read a non-volatile memory

ALAMELDEEN ALAA R

Hardware support for thread scheduling on multi-core processors

Dynamically allocatable memory error mitigation

Cache memory data compression and decompression

WILKERSON CHRISTOPHER B

Method and apparatus for using cache memory in a system that supports a low power state

Adaptive self-repairing cache

WISCONSIN ALUMNI RES FOUND

Adaptive cache compression system

CHISHTI ZESHAN A

Performing multi-bit error correction on a cache line

KHELLAH MUHAMMAD M

Reducing minimum operating voltage through hybrid cache design

SHA TINGTING

Compiler assisted low power and high performance load handling based on load types