Inventor

SHI LEATHEN

US52 patents

⚠️ This page may combine multiple inventors who share the name “SHI LEATHEN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SHI LEATHEN

IBM

Self-aligned SOI with different crystal orientation using wafer bonding and SIMOX processes

Method of forming a fully-depleted SOI ( silicon-on-insulator) MOSFET having a thinned channel region

Three dimensional high performance interconnection package

Accurate control of distance between suspended semiconductor nanowires and substrate surface

Strained silicon CMOS on hybrid crystal orientations

Fully-depleted SOI MOSFETs with low source and drain resistance and minimal overlap capacitance using a recessed channel damascene gate process

Flip-Chip interconnections using lead-free solders

Method of forming a three dimensional high performance interconnection package

Method of fabricating silicon devices on sapphire with wafer bonding at low temperature

Solder/polymer composite paste and method

Method of creating defect free high Ge content (&gt;25%) SiGe-on-insulator (SGOI) substrates using wafer bonding techniques

Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI)

SOI wafers with 30-100 Å buried oxide (BOX) created by wafer bonding using 30-100 Å thin oxide as bonding layer

Back-gated fully depleted SOI transistor

Mechanical packaging and thermal management of flat mirror arrays

Mechanical packaging and thermal management of flat mirror arrays

Non-destructive flex testing method and means

Encapsulated MEMS band-pass filter for integrated circuits and method of fabrication thereof

Encapsulated MEMS brand-pass filter for integrated circuits

Damascene double-gate MOSFET structure and its fabrication method

Method for preparing 2-dimensional semiconductor devices for integration in a third dimension

Low cost fabrication of double box back gate silicon-on-insulator wafers with built-in shallow trench isolation in back gate layer

Strained silicon CMOS on hybrid crystal orientations

Self-aligned SOI with different crystal orientation using WAFER bonding and SIMOX processes

Semiconductor device including built-in crack-arresting film structure

Method of creating defect free high Ge content (&gt;25%) SiGe-on-insulator (SGOI) substrates using wafer bonding techniques

Method of creating defect free high Ge content (&gt; 25%) SiGe-on-insulator (SGOI) substrates using wafer bonding techniques

Asymmetric studs and connecting lines to minimize stress

Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI)

Accurate control of distance between suspended semiconductor nanowires and substrate surface

Low-cost strained SOI substrate for high-performance CMOS technology

SOI wafers with 30-100 Å buried oxide (BOX) created by wafer bonding using 30-100 Å thin oxide as bonding layer

Preparation of high quality strained-semiconductor directly-on-insulator substrates

Low temperature fusion bonding with high surface energy using a wet chemical treatment

Semiconductor device including built-in crack-arresting film structure

Semiconductor device including built-in crack-arresting film structure

Semiconductor device including built-in crack-arresting film structure

Epitaxial lift-off process with guided etching

Epitaxial lift-off process with guided etching

Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI)

Strained silicon CMOS on hybrid crystal orientations

Multiple layer and crystal plane orientation semiconductor substrate

Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI)

DENNARD ROBERT H

Isolation structures for SOI devices with ultrathin SOI and ultrathin box

Low cost fabrication of double box back gate silicon-on-insulator wafers with subsequent self aligned shallow trench isolation

Method of forming isolation structures for SOI devices with ultrathin SOI and ultrathin box

GLOBALFOUNDRIES INC

Flattened substrate surface for substrate bonding

COONEY III EDWARD C

Flattened substrate surface for substrate bonding

GUO DECHAO

Adaptive chuck for planar bonding between substrates

LEOBANDUNG EFFENDI

High-k dielectric and silicon nitride box region

Method of creating defect free high Ge content (>25%) SiGe-on-insulator (SGOI) substrates using wafer bonding techniques

Method of creating defect free high Ge content (>25%) SiGe-on-insulator (SGOI) substrates using wafer bonding techniques

Method of creating defect free high Ge content (> 25%) SiGe-on-insulator (SGOI) substrates using wafer bonding techniques