Inventor
DUNCAN SAMUEL HAMMOND
US19 patents
⚠️ This page may combine multiple inventors who share the name “DUNCAN SAMUEL HAMMOND”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
NVIDIA CORP
9 patentsUS7685371B1Mar 23, 2010
Hierarchical flush barrier mechanism with deadlock avoidance
NVIDIA CORP9 citations83
US7685370B1Mar 23, 2010
Data synchronization with multiple producers
NVIDIA CORP16 citations83
US7469309B1Dec 23, 2008
Peer-to-peer data transfer method and apparatus with request limits
NVIDIA CORP19 citations81
US9858221B2Jan 2, 2018
Producer/consumer remote synchronization
NVIDIA CORP2 citations71
US10769076B2Sep 8, 2020
Distributed address translation in a multi-node interconnect fabric
NVIDIA CORP3 citations69
US11327900B2May 10, 2022
Securing memory accesses in a virtualized environment
NVIDIA CORP0 citations59
US8380896B2Feb 19, 2013
Data packer for packing and aligning write data
NVIDIA CORP0 citations50
US8380895B2Feb 19, 2013
Data packer for packing and aligning write data
NVIDIA CORP0 citations50
US10114760B2Oct 30, 2018
Method and system for implementing multi-stage translation of virtual addresses
NVIDIA CORP0 citations41
DIGITAL EQUIPMENT CORP
3 patentsUS5953538ASep 14, 1999
Method and apparatus providing DMA transfers between devices coupled to different host bus bridges
DIGITAL EQUIPMENT CORP179 citations96
US6012120AJan 4, 2000
Method and apparatus for providing DMA transfers between devices coupled to different host bus bridges
DIGITAL EQUIPMENT CORP54 citations93
US5822195AOct 13, 1998
Interface that permits data bus signals to pass between high frequency processing unit and low frequency expansion devices
DIGITAL EQUIPMENT CORP35 citations85
WONG RAYMOND HOI MAN
3 patentsCOMPAQ COMPUTER CORP
2 patentsUS6353877B1Mar 5, 2002
Performance optimization and system bus duty cycle reduction by I/O bridge partial cache line write
COMPAQ COMPUTER CORP70 citations92
US6128711AOct 3, 2000
Performance optimization and system bus duty cycle reduction by I/O bridge partial cache line writes
COMPAQ COMPUTER CORP34 citations89