Inventor

ASHBAUGH BEN J

US50 patents

⚠️ This page may combine multiple inventors who share the name “ASHBAUGH BEN J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ASHBAUGH BEN J

INTEL CORP

Compute unit having independent data paths

Mixed inference using low and high precision

Instructions having support for floating point and integer data types in the same register

Autonomous vehicle advanced sensing and response

Compute optimizations for low precision machine learning operations

Instruction based control of memory attributes

Compute optimizations for low precision machine learning operations

Compute optimizations for low precision machine learning operations

Compute optimization mechanism for deep neural networks

Extend GPU/CPU coherency to multi-GPU cores

Compute optimization mechanism for deep neural networks

Concurrent multi-datatype execution within a processing resource

Convolutional neural network optimization mechanism

Implicit fence for write messages

Compute optimizations for low precision machine learning operations

Compute optimization mechanism for deep neural networks

Extend GPU/CPU coherency to multi-GPU cores

Compute optimization mechanism for deep neural networks

Intelligent thread dispatch and vectorization of atomic operations

Extend GPU/CPU coherency to multi-GPU cores

Intelligent thread dispatch and vectorization of atomic operations

Autonomous vehicle advanced sensing and response

Facilitating execution-aware hybrid preemption for execution of tasks in computing environments

Compute optimization mechanism for deep neural networks

Extend GPU/CPU coherency to multi-GPU cores

Compute optimization mechanism for deep neural networks

Compute optimization mechanism for deep neural networks

Intelligent thread dispatch and vectorization of atomic operations

Compute optimization mechanism for deep neural networks

Compute optimization mechanism for deep neural networks

Low power inference engine pipeline in a graphics processing unit

Multicore processor with each core having independent floating point datapath and integer datapath

Neural network optimization mechanism

Compute optimizations for low precision machine learning operations

Compute optimizations for low precision machine learning operations

Convolutional neural network optimization mechanism

Compute optimizations for low precision machine learning operations

Convolutional neural network optimization mechanism

Compute optimizations for low precision machine learning operations

Compute optimizations for low precision machine learning operations

Autonomous vehicle advanced sensing and response

Providing native support for generic pointers in a graphics processing unit

Barrier state save and restore for preemption in a graphics environment

Compute optimization mechanism for deep neural networks

Method and apparatus to facilitate shared pointers in a heterogeneous platform

Method and apparatus to facilitate shared pointers in a heterogeneous platform

System and method to support multiple walkers per command

NI YANG

Method and apparatus to facilitate shared pointers in a heterogeneous platform

JANCZAK TOMASZ

Register allocation with SIMD architecture using write masks

ALTERA CORP

Incremental just-in-time (JIT) performance refinement for programmable logic device offload