Inventor

JAHAGIRDAR SANJEEV

US91 patents

⚠️ This page may combine multiple inventors who share the name “JAHAGIRDAR SANJEEV”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

JAHAGIRDAR SANJEEV

INTEL CORP

Instructions and logic to perform floating point and integer operations for machine learning

Instructions and logic to perform floating-point and integer operations for machine learning

Instructions and logic to perform floating point and integer operations for machine learning

Instructions and logic to perform floating-point and integer operations for machine learning

Instructions and logic to perform floating-point and integer operations for machine learning

Coordination and increased utilization of graphics processors during inference

Disaggregation of SOC architecture

Method and apparatus for accurate on-die temperature measurement

Method and apparatus for a zero voltage processor sleep state

Method and apparatus for a zero voltage processor sleep state

Method, apparatus, and system for increasing single core performance in a multi-core microprocessor

Method and apparatus for establishing safe processor operating points in connection with a secure boot

Power savings for neural network architecture with zero activations during inference

Method, apparatus, and system for optimizing frequency and performance in a multi-die microprocessor

Method, apparatus and system to dynamically choose an aoptimum power state

Method, apparatus, and system for optimizing frequency and performance in a multidie microprocessor

Method and apparatus for improved reliability and reduced power in a processor by automatic voltage control during processor idle states

Maintaining processor execution during frequency transitioning

Systems and methods for cache optimization

Graphics processing unit processing and caching improvements

Efficient thread group scheduling

Disaggregation of system-on-chip (SOC) architecture

Disaggregation of System-On-Chip (SOC) architecture

Person tracking and privacy and acceleration of data using autonomous machines

Method, system, and apparatus for dynamically configuring the operating point utilized for thermal management of an integrated circuit

Method, apparatus and system to dynamically choose an optimum power state

Resource load balancing based on usage and power limits

Systems and methods for cache optimization

Systems and methods for cache optimization

Dynamic distributed training of machine learning models

Instructions and logic to perform floating point and integer operations for machine learning

Hybrid graphics processor-field programmable gate array system

Barriers and synchronization for machine learning at autonomous machines

Data operations and finite state machine for machine learning via bypass of computational tasks based on frequently-used data values

Coordination and increased utilization of graphics processors during inference

Intelligent thread dispatch and vectorization of atomic operations

Intelligent thread dispatch and vectorization of atomic operations

Independently controlling frequency of plurality of power domains in a processor system

Enabling product SKUS based on chiplet configurations

Enabling product SKUs based on chiplet configurations

Dynamic power budget allocation in multi-processor system

Preconditioning of source data for packed min/max instructions

System and method for initiating a reduced power mode for one or more functional blocks of a processor based on various types of mode request

Apparatus and method of balancing input power from multiple sources

WELLS RYAN D

System, method and apparatus for energy efficiency and energy conservation by configuring power management parameters during run time

System, method and apparatus for energy efficiency and energy conservation by configuring power management parameters during run time

Method, apparatus, and system for energy efficiency and energy conservation including enhanced temperature based voltage control

JAHAGIRDAR SANJEEV

Method and apparatus for powered off processor core mode

Technique for preserving cached information during a low power mode

ALLAREY JOSE

Method and apparatus for a zero voltage processor sleep state