Inventor
RANGANATHAN VASANTH
US165 patents
Patents
50 patentsUS11360767B2Jun 14, 2022
Instructions and logic to perform floating point and integer operations for machine learning
INTEL CORP39 citations98
US11169799B2Nov 9, 2021
Instructions and logic to perform floating-point and integer operations for machine learning
INTEL CORP36 citations98
US11080046B2Aug 3, 2021
Instructions and logic to perform floating point and integer operations for machine learning
INTEL CORP38 citations98
US10474458B2Nov 12, 2019
Instructions and logic to perform floating-point and integer operations for machine learning
INTEL CORP46 citations98
US10353706B2Jul 16, 2019
Instructions and logic to perform floating-point and integer operations for machine learning
INTEL CORP47 citations98
US10304154B2May 28, 2019
Coordination and increased utilization of graphics processors during inference
INTEL CORP33 citations98
US11620256B2Apr 4, 2023
Systems and methods for improving cache efficiency and utilization
INTEL CORP36 citations97
US11113784B2Sep 7, 2021
Sparse optimizations for a matrix accelerator architecture
INTEL CORP46 citations97
US12204487B2Jan 21, 2025
Graphics processor data access and sharing
INTEL CORP2 citations86
US12182035B2Dec 31, 2024
Systems and methods for cache optimization
INTEL CORP6 citations86
US11861761B2Jan 2, 2024
Graphics processing unit processing and caching improvements
INTEL CORP8 citations86
US11842423B2Dec 12, 2023
Dot product operations on sparse matrix elements
INTEL CORP4 citations86
US11663746B2May 30, 2023
Systolic arithmetic on sparse data
INTEL CORP12 citations86
US11360808B2Jun 14, 2022
Efficient thread group scheduling
INTEL CORP8 citations86
US12210477B2Jan 28, 2025
Systems and methods for improving cache efficiency and utilization
INTEL CORP2 citations85
US12013808B2Jun 18, 2024
Multi-tile architecture for graphics operations
INTEL CORP3 citations85
US11954062B2Apr 9, 2024
Dynamic memory reconfiguration
INTEL CORP3 citations85
US11755501B2Sep 12, 2023
Efficient data sharing for graphics data processing operations
INTEL CORP9 citations85
US11676239B2Jun 13, 2023
Sparse optimizations for a matrix accelerator architecture
INTEL CORP10 citations85
US12182062B1Dec 31, 2024
Multi-tile memory management
INTEL CORP2 citations84
US12141094B2Nov 12, 2024
Systolic disaggregation within a matrix accelerator architecture
INTEL CORP2 citations84
US11995029B2May 28, 2024
Multi-tile memory management for detecting cross tile access providing multi-tile inference scaling and providing page migration
INTEL CORP2 citations84
US11157283B2Oct 26, 2021
Instruction prefetch based on thread dispatch commands
INTEL CORP5 citations84
US11145105B2Oct 12, 2021
Multi-tile graphics processor rendering
INTEL CORP6 citations84
US10909039B2Feb 2, 2021
Data prefetching for graphics data processing
INTEL CORP5 citations84
US10303953B2May 28, 2019
Person tracking and privacy and acceleration of data using autonomous machines
INTEL CORP6 citations84
US12066975B2Aug 20, 2024
Cache structure and utilization
INTEL CORP2 citations82
US10424107B2Sep 24, 2019
Hierarchical depth buffer back annotaton
INTEL CORP5 citations81
US12124383B2Oct 22, 2024
Systems and methods for cache optimization
INTEL CORP3 citations75
US12056059B2Aug 6, 2024
Systems and methods for cache optimization
INTEL CORP3 citations75
US11797837B2Oct 24, 2023
Dynamic distributed training of machine learning models
INTEL CORP4 citations75
US11934342B2Mar 19, 2024
Assistance for hardware prefetch in cache access
INTEL CORP3 citations74
US12561276B2Feb 24, 2026
Systems and methods for updating memory side caches in a multi-GPU configuration
INTEL CORP0 citations73
US12386779B2Aug 12, 2025
Dynamic memory reconfiguration
INTEL CORP0 citations73
US12242414B2Mar 4, 2025
Data initialization techniques
INTEL CORP0 citations73
US12153541B2Nov 26, 2024
Cache structure and utilization
INTEL CORP0 citations73
US12141578B2Nov 12, 2024
Instructions and logic to perform floating point and integer operations for machine learning
INTEL CORP2 citations73
US12099461B2Sep 24, 2024
Multi-tile memory management
INTEL CORP0 citations73
US11494868B2Nov 8, 2022
Contextual configuration adjuster for graphics
INTEL CORP1 citations73
US11393211B2Jul 19, 2022
Hybrid graphics processor-field programmable gate array system
INTEL CORP1 citations73
US11354848B1Jun 7, 2022
Motion biased foveated renderer
INTEL CORP1 citations73
US11353868B2Jun 7, 2022
Barriers and synchronization for machine learning at autonomous machines
INTEL CORP3 citations73
US11269643B2Mar 8, 2022
Data operations and finite state machine for machine learning via bypass of computational tasks based on frequently-used data values
INTEL CORP3 citations73
US11263141B2Mar 1, 2022
Sector cache for compression
INTEL CORP2 citations73
US11119820B2Sep 14, 2021
Local memory sharing between kernels
INTEL CORP3 citations73
US11010659B2May 18, 2021
Dynamic precision for neural network compute operations
INTEL CORP2 citations73
US10929947B2Feb 23, 2021
Contextual configuration adjuster for graphics
INTEL CORP2 citations73
US10891707B2Jan 12, 2021
Coordination and increased utilization of graphics processors during inference
INTEL CORP1 citations73
US10878614B2Dec 29, 2020
Motion biased foveated renderer
INTEL CORP3 citations73
US10871966B2Dec 22, 2020
Intelligent thread dispatch and vectorization of atomic operations
INTEL CORP4 citations73
Showing the top 50 of 165 patents by PatentIndex Score.