Inventor

LIE SEAN

US39 patents

⚠️ This page may combine multiple inventors who share the name “LIE SEAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LIE SEAN

CEREBRAS SYSTEMS INC

Accelerated deep learning

Backpressure for accelerated deep learning

Dataflow triggered tasks for accelerated deep learning

Wavelet representation for accelerated deep learning

Task synchronization for accelerated deep learning

Data structure descriptors for deep learning acceleration

Accelerated deep learning

Accelerated deep learning

Neuron smearing for accelerated deep learning

Floating-point unit stochastic rounding for accelerated deep learning

Processor element redundancy for accelerated deep learning

Scaled compute fabric for accelerated deep learning

Fabric vectors for deep learning acceleration

Data structure descriptors for deep learning acceleration

Numerical representation for neural networks

Control wavelet for accelerated deep learning

Data structure descriptors for deep learning acceleration

Microthreading for accelerated deep learning

Task activating for accelerated deep learning

Control wavelet for accelerated deep learning

Task activating for accelerated deep learning

ISA enhancements for accelerated deep learning

Dynamic routing for accelerated deep learning

Task synchronization for accelerated deep learning

Advanced wavelet filtering for accelerated deep learning

Basic wavelet filtering for accelerated deep learning

Placement of compute and memory for accelerated deep learning

GLOBALFOUNDRIES INC

Mechanism for using performance counters to identify reasons and delay times for instructions that are stalled during retirement

Method and apparatus for length decoding variable length instructions

Processing pipeline having parallel dispatch and method thereof

Immediate and displacement extraction and decode mechanism

Method and apparatus for length decoding and identifying boundaries of variable length instructions

ADVANCED MICRO DEVICES INC

Multiple-core processor with hierarchical microcode store

Distributed dispatch with concurrent, out-of-order dispatch

Thin provisioning architecture for high seek-time devices

Hop-by-hop error detection in a server system

GLOBAL FOUNDRIES INC

Redirect recovery cache that receives branch misprediction redirects and caches instructions to be dispatched in response to the redirects

LIE SEAN

Distributed packet switching in a source routed cluster server

SHEN GENE

Processing pipeline having stage-specific thread selection and method thereof