Inventor

LAUTERBACH GARY R

US43 patents

⚠️ This page may combine multiple inventors who share the name “LAUTERBACH GARY R”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LAUTERBACH GARY R

CEREBRAS SYSTEMS INC

Accelerated deep learning

Backpressure for accelerated deep learning

Dataflow triggered tasks for accelerated deep learning

Wavelet representation for accelerated deep learning

Task synchronization for accelerated deep learning

Data structure descriptors for deep learning acceleration

Accelerated deep learning

Accelerated deep learning

Neuron smearing for accelerated deep learning

Floating-point unit stochastic rounding for accelerated deep learning

Processor element redundancy for accelerated deep learning

Scaled compute fabric for accelerated deep learning

Fabric vectors for deep learning acceleration

Data structure descriptors for deep learning acceleration

Numerical representation for neural networks

Data structure descriptors for deep learning acceleration

Control wavelet for accelerated deep learning

Microthreading for accelerated deep learning

Task activating for accelerated deep learning

Control wavelet for accelerated deep learning

Task activating for accelerated deep learning

ISA enhancements for accelerated deep learning

Dynamic routing for accelerated deep learning

Task synchronization for accelerated deep learning

Advanced wavelet filtering for accelerated deep learning

Basic wavelet filtering for accelerated deep learning

Placement of compute and memory for accelerated deep learning

SUN MICROSYSTEMS INC

Low-latency memory indexing method and structure

Integrated circuit assembly module that supports capacitive communication between semiconductor dies

Packaging for proximity communication positioned integrated circuits

Execution unit and method for executing performance critical and non-performance critical arithmetic instructions in separate pipelines

Microprocessor configured to generate help instructions for performing data cache fills

Method and apparatus for designing a circuit by analyzing selected artificial hardware dependencies inserted into a dynamic dependency graph

Computer system architecture using a proximity I/O switch

Computer system architecture using a proximity I/O switch

Method for handling data cache misses using help instructions

Active socket for facilitating proximity communication

Execution unit and method for using architectural and working register files to reduce operand bypasses

ACRISON INC

Weigh feeding apparatus

Weigh feeding apparatus

ORACLE AMERICA INC

Replicated service architecture

LIE SEAN

Distributed packet switching in a source routed cluster server

DROST ROBERT J

Method for manufacturing an active socket for facilitating proximity communication