Inventor
SELVIDGE CHARLES W
US32 patents
⚠️ This page may combine multiple inventors who share the name “SELVIDGE CHARLES W”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
MENTOR GRAPHICS CORP
18 patentsUS7480610B2Jan 20, 2009
Software state replay
MENTOR GRAPHICS CORP28 citations91
US7143377B1Nov 28, 2006
Functional verification of logic and memory circuits with multiple asynchronous domains
MENTOR GRAPHICS CORP37 citations91
US9767237B2Sep 19, 2017
Target capture and replay in emulation
MENTOR GRAPHICS CORP16 citations90
US6961691B1Nov 1, 2005
Non-synchronized multiplex data transport across synchronous systems
MENTOR GRAPHICS CORP19 citations89
US8843861B2Sep 23, 2014
Third party component debugging for integrated circuit design
MENTOR GRAPHICS CORP8 citations84
US9898563B2Feb 20, 2018
Modeling memory in emulation based on cache
MENTOR GRAPHICS CORP2 citations72
US9703579B2Jul 11, 2017
Debug environment for a multi user hardware assisted verification system
MENTOR GRAPHICS CORP4 citations72
US10410713B1Sep 10, 2019
Content addressable memory modeling in emulation and prototyping
MENTOR GRAPHICS CORP3 citations71
US11113441B1Sep 7, 2021
Reduce/broadcast computation-enabled switching elements in an emulation network
MENTOR GRAPHICS CORP3 citations68
US10579776B1Mar 3, 2020
Selective conditional stall for hardware-based circuit design verification
MENTOR GRAPHICS CORP3 citations67
US7454722B2Nov 18, 2008
Acyclic modeling of combinational loops
MENTOR GRAPHICS CORP4 citations63
US9619600B2Apr 11, 2017
Third party component debugging for integrated circuit design
MENTOR GRAPHICS CORP1 citations51
US10664563B2May 26, 2020
Concurrent testbench and software driven verification
MENTOR GRAPHICS CORP1 citations50
US10503848B2Dec 10, 2019
Target capture and replay in emulation
MENTOR GRAPHICS CORP0 citations50
US9165099B2Oct 20, 2015
Adaptive clock management in emulation
MENTOR GRAPHICS CORP0 citations50
US10664566B2May 26, 2020
Bandwidth test in networking System-on-Chip verification
MENTOR GRAPHICS CORP0 citations48
US10657217B2May 19, 2020
Latency test in networking system-on-chip verification
MENTOR GRAPHICS CORP0 citations48
US9305126B2Apr 5, 2016
Switching activity reduction through retiming
MENTOR GRAPHICS CORP0 citations40
VIRTUAL MACHINE WORKS INC
4 patentsUS5649176AJul 15, 1997
Transition analysis and circuit resynthesis method and device for digital circuit modeling
VIRTUAL MACHINE WORKS INC202 citations97
US5850537ADec 15, 1998
Pipe lined static router and scheduler for configurable logic system performing simultaneous communications and computation
VIRTUAL MACHINE WORKS INC90 citations94
US5659716AAug 19, 1997
Pipe-lined static router and scheduler for configurable logic system performing simultaneous communications and computation
VIRTUAL MACHINE WORKS INC81 citations94
US5802348ASep 1, 1998
Logic analysis system for logic emulation systems
VIRTUAL MACHINE WORKS INC49 citations93