Inventor
ESPIG MICHAEL
US21 patents
⚠️ This page may combine multiple inventors who share the name “ESPIG MICHAEL”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
19 patentsUS10719323B2Jul 21, 2020
Systems and methods for performing matrix compress and decompress instructions
INTEL CORP56 citations98
US10896043B2Jan 19, 2021
Systems for performing instructions for fast element unpacking into 2-dimensional registers
INTEL CORP34 citations95
US10922077B2Feb 16, 2021
Apparatuses, methods, and systems for stencil configuration and computation instructions
INTEL CORP23 citations94
US10942985B2Mar 9, 2021
Apparatuses, methods, and systems for fast fourier transform configuration and computation instructions
INTEL CORP25 citations92
US11886875B2Jan 30, 2024
Systems and methods for performing nibble-sized operations on matrix elements
INTEL CORP7 citations86
US11847185B2Dec 19, 2023
Systems and methods of instructions to accelerate multiplication of sparse matrices using bitmasks that identify non-zero elements
INTEL CORP7 citations86
US11748103B2Sep 5, 2023
Systems and methods for performing matrix compress and decompress instructions
INTEL CORP9 citations86
US11507376B2Nov 22, 2022
Systems for performing instructions for fast element unpacking into 2-dimensional registers
INTEL CORP10 citations86
US11294671B2Apr 5, 2022
Systems and methods for performing duplicate detection instructions on 2D data
INTEL CORP8 citations86
US11249761B2Feb 15, 2022
Systems and methods for performing matrix compress and decompress instructions
INTEL CORP11 citations86
US12175246B2Dec 24, 2024
Systems and methods for performing matrix compress and decompress instructions
INTEL CORP1 citations73
US12287843B2Apr 29, 2025
Systems and methods of instructions to accelerate multiplication of sparse matrices using bitmasks that identify non-zero elements
INTEL CORP1 citations64
US12099838B2Sep 24, 2024
Instruction and logic for sum of square differences
INTEL CORP0 citations60
US12321714B2Jun 3, 2025
Compressed wallace trees in FMA circuits
INTEL CORP0 citations58
US11836464B2Dec 5, 2023
Method and apparatus for efficient binary and ternary support in fused multiply-add (FMA) circuits
INTEL CORP0 citations58
US11366636B2Jun 21, 2022
Method and apparatus for efficient binary and ternary support in fused multiply-add (FMA) circuits
INTEL CORP0 citations58
US11327754B2May 10, 2022
Method and apparatus for approximation using polynomials
INTEL CORP0 citations52
US10713012B2Jul 14, 2020
Method and apparatus for efficient binary and ternary support in fused multiply-add (FMA) circuits
INTEL CORP0 citations47
US12182570B2Dec 31, 2024
Apparatuses, methods, and systems for a packed data convolution instruction with shift control and width control
INTEL CORP0 citations46