Inventor
BAUM DAN
IL49 patents
⚠️ This page may combine multiple inventors who share the name “BAUM DAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
47 patentsUS11163565B2Nov 2, 2021
Systems, methods, and apparatuses for dot production operations
INTEL CORP24 citations98
US11086623B2Aug 10, 2021
Systems, methods, and apparatuses for tile matrix multiplication and accumulation
INTEL CORP32 citations98
US10990396B2Apr 27, 2021
Systems for performing instructions to quickly convert and use tiles as 1D vectors
INTEL CORP32 citations98
US10877756B2Dec 29, 2020
Systems, methods, and apparatuses for tile diagonal
INTEL CORP16 citations98
US10719323B2Jul 21, 2020
Systems and methods for performing matrix compress and decompress instructions
INTEL CORP56 citations98
US10896043B2Jan 19, 2021
Systems for performing instructions for fast element unpacking into 2-dimensional registers
INTEL CORP34 citations95
US12039332B2Jul 16, 2024
Systems, methods, and apparatus for matrix move
INTEL CORP7 citations94
US11977886B2May 7, 2024
Systems, methods, and apparatuses for tile store
INTEL CORP7 citations94
US11847452B2Dec 19, 2023
Systems, methods, and apparatus for tile configuration
INTEL CORP7 citations94
US11714642B2Aug 1, 2023
Systems, methods, and apparatuses for tile store
INTEL CORP7 citations94
US11567765B2Jan 31, 2023
Systems, methods, and apparatuses for tile load
INTEL CORP8 citations94
US11288068B2Mar 29, 2022
Systems, methods, and apparatus for matrix move
INTEL CORP7 citations94
US11288069B2Mar 29, 2022
Systems, methods, and apparatuses for tile store
INTEL CORP7 citations94
US11263008B2Mar 1, 2022
Systems, methods, and apparatuses for tile broadcast
INTEL CORP7 citations94
US11200055B2Dec 14, 2021
Systems, methods, and apparatuses for matrix add, subtract, and multiply
INTEL CORP14 citations94
US11080048B2Aug 3, 2021
Systems, methods, and apparatus for tile configuration
INTEL CORP14 citations94
US10970076B2Apr 6, 2021
Systems and methods for performing instructions specifying ternary tile logic operations
INTEL CORP27 citations94
US11954489B2Apr 9, 2024
Systems for performing instructions to quickly convert and use tiles as 1D vectors
INTEL CORP9 citations86
US11886875B2Jan 30, 2024
Systems and methods for performing nibble-sized operations on matrix elements
INTEL CORP7 citations86
US11847185B2Dec 19, 2023
Systems and methods of instructions to accelerate multiplication of sparse matrices using bitmasks that identify non-zero elements
INTEL CORP7 citations86
US11748103B2Sep 5, 2023
Systems and methods for performing matrix compress and decompress instructions
INTEL CORP9 citations86
US11714648B2Aug 1, 2023
Systems for performing instructions to quickly convert and use tiles as 1D vectors
INTEL CORP9 citations86
US11579883B2Feb 14, 2023
Systems and methods for performing horizontal tile operations
INTEL CORP17 citations86
US11579880B2Feb 14, 2023
Systems for performing instructions to quickly convert and use tiles as 1D vectors
INTEL CORP9 citations86
US11507376B2Nov 22, 2022
Systems for performing instructions for fast element unpacking into 2-dimensional registers
INTEL CORP10 citations86
US11294671B2Apr 5, 2022
Systems and methods for performing duplicate detection instructions on 2D data
INTEL CORP8 citations86
US11249761B2Feb 15, 2022
Systems and methods for performing matrix compress and decompress instructions
INTEL CORP11 citations86
US10838734B2Nov 17, 2020
Apparatus and method for processing structure of arrays (SoA) and array of structures (AoS) data
INTEL CORP8 citations84
US12260213B2Mar 25, 2025
Systems, methods, and apparatuses for matrix add, subtract, and multiply
INTEL CORP1 citations75
US12536020B2Jan 27, 2026
Systems, methods, and apparatuses for tile store
INTEL CORP0 citations73
US12314717B2May 27, 2025
Systems, methods, and apparatuses for dot production operations
INTEL CORP0 citations73
US12282773B2Apr 22, 2025
Systems, methods, and apparatus for tile configuration
INTEL CORP0 citations73
US12182571B2Dec 31, 2024
Systems, methods, and apparatuses for tile load, multiplication and accumulation
INTEL CORP0 citations73
US12175246B2Dec 24, 2024
Systems and methods for performing matrix compress and decompress instructions
INTEL CORP1 citations73
US12147804B2Nov 19, 2024
Systems, methods, and apparatuses for tile matrix multiplication and accumulation
INTEL CORP1 citations73
US12124847B2Oct 22, 2024
Systems, methods, and apparatuses for tile transpose
INTEL CORP0 citations73
US12106100B2Oct 1, 2024
Systems, methods, and apparatuses for matrix operations
INTEL CORP0 citations73
US12032485B2Jul 9, 2024
64-bit virtual addresses having metadata bit(s) and canonicality check that does not fail due to non-canonical values of metadata bit(s)
INTEL CORP2 citations73
US12287843B2Apr 29, 2025
Systems and methods of instructions to accelerate multiplication of sparse matrices using bitmasks that identify non-zero elements
INTEL CORP1 citations64
US12461745B2Nov 4, 2025
Systems for performing instructions to quickly convert and use tiles as 1D vectors
INTEL CORP0 citations63
US12265826B2Apr 1, 2025
Systems for performing instructions to quickly convert and use tiles as 1D vectors
INTEL CORP0 citations63
US11422809B2Aug 23, 2022
Apparatus and method for multicasting a cache line update using delayed refetch messages
INTEL CORP0 citations63
US10664273B2May 26, 2020
Delayed prefetch manager to multicast an updated cache line to processor cores requesting the updated data
INTEL CORP1 citations63
US11327754B2May 10, 2022
Method and apparatus for approximation using polynomials
INTEL CORP0 citations52
US12277234B2Apr 15, 2025
Cryptographic computing in multitenant environments
INTEL CORP0 citations51
US10509846B2Dec 17, 2019
Accelerator for processing data
INTEL CORP0 citations51
US8386807B2Feb 26, 2013
Power management for processing unit
INTEL CORP0 citations36