Inventor
KP SAMEER
IN31 patents
⚠️ This page may combine multiple inventors who share the name “KP SAMEER”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
30 patentsUS10380039B2Aug 13, 2019
Apparatus and method for memory management in a graphics processing environment
INTEL CORP17 citations94
US10109078B1Oct 23, 2018
Controlling coarse pixel size from a stencil buffer
INTEL CORP5 citations84
US11650658B2May 16, 2023
Compensating for high head movement in head-mounted displays
INTEL CORP9 citations83
US10649521B2May 12, 2020
Compensating for high head movement in head-mounted displays
INTEL CORP3 citations80
US11869119B2Jan 9, 2024
Controlling coarse pixel size from a stencil buffer
INTEL CORP2 citations73
US11360914B2Jun 14, 2022
Apparatus and method for memory management in a graphics processing environment
INTEL CORP1 citations73
US11354848B1Jun 7, 2022
Motion biased foveated renderer
INTEL CORP1 citations73
US10878614B2Dec 29, 2020
Motion biased foveated renderer
INTEL CORP3 citations73
US10769078B2Sep 8, 2020
Apparatus and method for memory management in a graphics processing environment
INTEL CORP1 citations73
US10706591B2Jul 7, 2020
Controlling coarse pixel size from a stencil buffer
INTEL CORP1 citations73
US10643374B2May 5, 2020
Positional only shading pipeline (POSH) geometry data processing with coarse Z buffer
INTEL CORP3 citations73
US10152822B2Dec 11, 2018
Motion biased foveated renderer
INTEL CORP3 citations73
US10134360B2Nov 20, 2018
Compressing the size of color lookup tables
INTEL CORP2 citations72
US11619987B2Apr 4, 2023
Compensating for high head movement in head-mounted displays
INTEL CORP2 citations71
US11237626B2Feb 1, 2022
Compensating for high head movement in head-mounted displays
INTEL CORP2 citations71
US12265439B2Apr 1, 2025
Co-existence of full frame and partial frame idle image updates
INTEL CORP0 citations62
US12243125B2Mar 4, 2025
Controlling coarse pixel size from a stencil buffer
INTEL CORP0 citations62
US11461959B2Oct 4, 2022
Positional only shading pipeline (POSH) geometry data processing with coarse Z buffer
INTEL CORP0 citations62
US11314310B2Apr 26, 2022
Co-existence of full frame and partial frame idle image updates
INTEL CORP0 citations62
US11244479B2Feb 8, 2022
Controlling coarse pixel size from a stencil buffer
INTEL CORP0 citations62
US12299189B2May 13, 2025
Compensating for high head movement in head-mounted displays
INTEL CORP0 citations60
US11907416B1Feb 20, 2024
Compensating for high head movement in head-mounted displays
INTEL CORP0 citations60
US9530386B2Dec 27, 2016
Methods and apparatus to provide extended graphics processing capabilities
INTEL CORP1 citations60
US11348511B2May 31, 2022
Enabling a chipset that supports a single display to support dual display
INTEL CORP0 citations53
US10867583B2Dec 15, 2020
Beam scanning image processing within an improved graphics processor micro architecture
INTEL CORP0 citations52
US10497340B2Dec 3, 2019
Beam scanning image processing within an improved graphics processor microarchitecture
INTEL CORP0 citations52
US9600055B2Mar 21, 2017
Intelligent power management for a multi-display mode enabled electronic device
INTEL CORP1 citations52
US10453429B2Oct 22, 2019
Methods and apparatus to provide extended graphics processing capabilities
INTEL CORP0 citations49
US10453430B2Oct 22, 2019
Methods and apparatus to provide extended graphics processing capabilities
INTEL CORP0 citations49
US10275924B2Apr 30, 2019
Techniques for managing three-dimensional graphics display modes
INTEL CORP0 citations31