Inventor
TAN TAT HIN
MY21 patents
⚠️ This page may combine multiple inventors who share the name “TAN TAT HIN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
13 patentsUS10903142B2Jan 26, 2021
Micro through-silicon via for transistor density scaling
INTEL CORP8 citations83
US9443567B1Sep 13, 2016
High speed sense amplifier latch with low power rail-to-rail input common mode range
INTEL CORP6 citations79
US10223483B1Mar 5, 2019
Methods for determining resistive-capacitive component design targets for radio-frequency circuitry
INTEL CORP7 citations76
US11652026B2May 16, 2023
Micro through-silicon via for transistor density scaling
INTEL CORP2 citations72
US11398415B2Jul 26, 2022
Stacked through-silicon vias for multi-device packages
INTEL CORP3 citations72
US10200046B1Feb 5, 2019
High resolution and low power interpolator for delay chain
INTEL CORP4 citations71
US10333689B2Jun 25, 2019
High speed sense amplifier latch with low power rail-to-rail input common mode range
INTEL CORP2 citations68
US12112997B2Oct 8, 2024
Micro through-silicon via for transistor density scaling
INTEL CORP0 citations62
US12080628B2Sep 3, 2024
Micro through-silicon via for transistor density scaling
INTEL CORP0 citations62
US11393741B2Jul 19, 2022
Micro through-silicon via for transistor density scaling
INTEL CORP0 citations62
US6967532B2Nov 22, 2005
Offset-compensated self-biased differential amplifier
INTEL CORP6 citations62
US10714163B2Jul 14, 2020
Methods for mitigating transistor aging to improve timing margins for memory interface signals
INTEL CORP1 citations57
US10110225B1Oct 23, 2018
Integrated circuit with an increased signal bandwidth input/output (I/O) circuit
INTEL CORP1 citations50
SKYECHIP SDN BHD
4 patentsUS11373694B1Jun 28, 2022
Generic physical layer providing a unified architecture for interfacing with an external memory device and methods of interfacing with an external memory device
SKYECHIP SDN BHD0 citations61
US12469541B2Nov 11, 2025
Offset calibration method and apparatus for high bandwidth memory 3 (HBM3)
SKYECHIP SDN BHD0 citations58
US12422883B2Sep 23, 2025
System and a method for aligning a programmable clock or strobe
SKYECHIP SDN BHD0 citations43
US11575383B2Feb 7, 2023
Clocking system and a method of clock synchronization
SKYECHIP SDN BHD0 citations43
ALTERA CORP
3 patentsUS10198545B1Feb 5, 2019
Systems and methods for extraction of electrical specifications from prelayout simulations
ALTERA CORP7 citations75
US9793888B2Oct 17, 2017
Techniques for enabling and disabling transistor legs in an output driver circuit
ALTERA CORP1 citations51
US10224911B1Mar 5, 2019
Dual signal protocol input/output (I/O) buffer circuit
ALTERA CORP0 citations39