Inventor

PRIYADARSHI SHIVAM

US29 patents

⚠️ This page may combine multiple inventors who share the name “PRIYADARSHI SHIVAM”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PRIYADARSHI SHIVAM

QUALCOMM INC

Storing narrow produced values for instruction operands directly in a register map in an out-of-order processor

Selective storing of previously decoded instructions of frequently-called instruction sequences in an instruction sequence buffer to be executed by a processor

Selective bypassing of allocation in a cache

Allocating power between multiple central processing units (CPUs) in a multi-CPU processor based on total current availability and individual CPU quality-of-service (QoS) requirements

Dynamic pipeline throttling using confidence-based weighting of in-flight branch instructions

Method, apparatus, and system for reducing live readiness calculations in reservation stations

Reducing memory access bandwidth based on prediction of memory request size

Method and apparatus for dynamic clock and voltage scaling in a computer processor based on program phase

Cost-aware cache replacement

Method and apparatus for dynamic clock and voltage scaling in a computer processor based on program phase

Providing late physical register allocation and early physical register release in out-of-order processor (OOP)-based devices implementing a checkpoint-based architecture

Reconfiguring execution pipelines of out-of-order (OOO) computer processors based on phase training and prediction

Providing references to previously decoded instructions of recently-provided instructions to be executed by a processor

Slice construction for pre-executing data dependent loads

Intelligent data prefetching using address delta prediction

MICROSOFT TECHNOLOGY LICENSING LLC

Recovering register mapping state of a flushed instruction employing a snapshot of another register mapping state and traversing reorder buffer (ROB) entries in a processor

Tracking exact convergence to guide the recovery process in response to a mispredicted branch

Performing flush recovery using parallel walks of sliced reorder buffers (SROBs)

Minimizing traversal of a processor reorder buffer (ROB) for register rename map table (RMT) state recovery for interrupted instruction recovery in a processor

Tracking exact convergence to guide the recovery process in response to a mispredicted branch

Limiting replay of load-based control independent (CI) instructions in speculative misprediction recovery in a processor

Systems and methods for processing instructions having wide immediate operands

Opportunistic consumer instruction steering based on producer instruction value prediction in a multi-cluster processor

Operand pool instruction reservation clustering in a scheduler circuit in a processor

Latency-based instruction reservation station clustering in a scheduler circuit in a processor

Restoring speculative history used for making speculative predictions for instructions processed in a processor employing control independence techniques

Predicting load-based control independent (CI) register data independent (DI) (CIRDI) instructions as CI memory data dependent (DD) (CIMDD) instructions for replay in speculative misprediction recovery in a processor

Deferring cache state updates in a non-speculative cache memory in a processor-based system in response to a speculative data request until the speculative data request becomes non-speculative

Enabling early execution of move-immediate instructions having variable immediate value sizes in processor-based devices