Inventor

KOTHINTI NARESH VIGNYAN REDDY

US21 patents

⚠️ This page may combine multiple inventors who share the name “KOTHINTI NARESH VIGNYAN REDDY”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KOTHINTI NARESH VIGNYAN REDDY

MICROSOFT TECHNOLOGY LICENSING LLC

Recovering register mapping state of a flushed instruction employing a snapshot of another register mapping state and traversing reorder buffer (ROB) entries in a processor

Tracking exact convergence to guide the recovery process in response to a mispredicted branch

Dynamic hammock branch training for branch hammock detection in an instruction stream executing in a processor

Minimizing traversal of a processor reorder buffer (ROB) for register rename map table (RMT) state recovery for interrupted instruction recovery in a processor

Tracking exact convergence to guide the recovery process in response to a mispredicted branch

Limiting replay of load-based control independent (CI) instructions in speculative misprediction recovery in a processor

Systems and methods for processing instructions having wide immediate operands

Opportunistic consumer instruction steering based on producer instruction value prediction in a multi-cluster processor

Operand pool instruction reservation clustering in a scheduler circuit in a processor

Tracking and communication of direct/indirect source dependencies of producer instructions executed in a processor to source dependent consumer instructions to facilitate processor optimizations

Restoring speculative history used for making speculative predictions for instructions processed in a processor employing control independence techniques

Predicting load-based control independent (CI) register data independent (DI) (CIRDI) instructions as CI memory data dependent (DD) (CIMDD) instructions for replay in speculative misprediction recovery in a processor

Deferring cache state updates in a non-speculative cache memory in a processor-based system in response to a speculative data request until the speculative data request becomes non-speculative

Enabling early execution of move-immediate instructions having variable immediate value sizes in processor-based devices

QUALCOMM INC

Selective storing of previously decoded instructions of frequently-called instruction sequences in an instruction sequence buffer to be executed by a processor

Selective flushing of instructions in an instruction pipeline in a processor back to an execution-resolved target address, in response to a precise interrupt

Providing predictive instruction dispatch throttling to prevent resource overflows in out-of-order processor (OOP)-based devices

Reduction of data cache access in a processing system

Deadlock free resource management in block based computing architectures

Providing variable interpretation of usefulness indicators for memory tables in processor-based systems

Reduced logic level operation folding of context history in a history register in a prediction system for a processor-based system