Inventor

LIU ERIC CHIH-FANG

US33 patents

⚠️ This page may combine multiple inventors who share the name “LIU ERIC CHIH-FANG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LIU ERIC CHIH-FANG

TOKYO ELECTRON LTD

Method and system for capping of cores for self-aligned multiple patterning

High aspect ratio via etch using atomic layer deposition protection layer

Forming a semiconductor feature using atomic layer etch

Method for reducing lithography defects and pattern transfer

Deposition process

Methods and structures for increasing stability of soft or organic features

Variable hardness amorphous carbon mask

Wet etch process and method to control fin height and channel area in a fin field effect transistor (FinFET)

Methods for planarizing a substrate using a combined wet etch and chemical mechanical polishing (CMP) process

Method for highly anisotropic etching of titanium oxide spacer using selective top-deposition

Method for reducing lithography defects and pattern transfer

Multiple patterning processes

Method of line cut by multi-color patterning technique

Manufacturing methods to apply stress engineering to self-aligned multi-patterning (SAMP) processes

Sacrificial gate capping layer for gate protection during source/drain contact opening

Method of self-aligned dielectric wall formation for forksheet application

Top-down self-alignment of vias in a semiconductor device for sub-22NM pitch metals

Methods for EUV inverse patterning in processing of microelectronic workpieces

Ruthenium metal feature fill for interconnects

Method for filling recessed features in semiconductor devices with a low-resistivity metal

Method for patterning a dielectric layer

Method for processing photoresist materials and structures

Wet etch process and methods to form air gaps between metal interconnects

Double patterning method of patterning a substrate

Double hardmasks for self-aligned multi-patterning processes

In-situ spacer reshaping for self-aligned multi-patterning methods and systems

Spacer formation for self-aligned multi-patterning technique

TAIWAN SEMICONDUCTOR MFG

FinFET device structure and methods of making same

FinFETs with regrown source/drain and methods for forming the same

Simultaneous formation of source/drain openings with different profiles

FinFET device structure and methods of making same

TAIWAN SEMICONDUCTOR MFG CO LTD

Process of manufacturing Fin-FET device

Simultaneous formation of source/drain openings with different profiles