Inventor

MOYER WILLIAM C

US302 patents

⚠️ This page may combine multiple inventors who share the name “MOYER WILLIAM C”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MOYER WILLIAM C

MOTOROLA INC

Method and apparatus for interfacing a processor to a coprocessor

Data processor with a privileged state firewall and method therefore

Method and apparatus for selecting a register file in a data processing system

Apparatus and method for optimizing performance of a cache memory in a data processing system

Bus master having burst transfer mode

Method and apparatus for affecting subsequent instruction processing in a data processor

Method and data processing system for dynamically accessing both big-endian and little-endian storage schemes

Data processor having selective breakpoint capability with minimal overhead

Data processor with concurrent static and dynamic masking of operand information and method therefor

Paged memory management unit which evaluates access permissions when creating translator

Paged memory management unit capable of selectively supporting multiple address spaces

Paged memory management unit capable of selectively supporting multiple address spaces

Virtual machine data processor

LCD driver module and method thereof

Method and apparatus for performing a snoop-retry protocol in a data processing system

Method and apparatus for performing bus arbitration in a data processing system

Low overhead method for selecting and updating an entry in a cache memory

MRAM cam

Charge conserving write method and system for an MRAM

Mram cam

Multi-way cache apparatus and method

Method and apparatus for controlling conditional branch execution in a data processor

Method and apparatus for controlling bus arbitration in a data processing system

Method and apparatus for selectively controlling interrupt latency in a data processing system

Data processing system for accessing an external device and method therefor

Method and apparatus for providing low power control of peripheral devices using the register file of a microprocessor

FREESCALE SEMICONDUCTOR INC

Method and apparatus for controlling a data processing system during debug

Bus arbitration in low power system

Error correction device and method thereof

Data processing system using independent memory and register operand size specifiers and method thereof

Method for powering an electronic device and circuit

Storage circuit with efficient sleep mode and method

Data processing system having address translation bypass and method therefor

Memory management circuitry translation information retrieval during debugging

Interfacing a processor to a coprocessor in which the processor selectively broadcasts to or selectively alters an execution mode of the coprocessor

Conditional next portion transferring of data stream to or from register based on subsequent instruction aspect

Real-time debug support for a DMA device and method thereof

Flexible interrupt controller that includes an interrupt force register

System and method for controlling bus arbitration during cache memory burst cycles

Data processing system and method for a sector cache

Apparatus and method for time ordering events in a system having multiple time domains

Data processing system with peripheral access protection and method therefor

Integrated circuit security and method therefor

Low power system and method for a data processing system

Arbiter having programmable arbitration points for undefined length burst accesses and method

Crossbar switch that supports a multi-port slave device and method of operation

MOYER WILLIAM C

Result forwarding to dependent instruction in pipelined processor with mode selectable execution in E1 or E2 of pipelined operational stages

Method and apparatus for loading or storing multiple registers in a data processing system

Qualification of conditional debug instructions based on address

RAMARAJU RAVINDRARAJ

Multi-core system on chip