Inventor
WU CHIH-I
TW21 patents
⚠️ This page may combine multiple inventors who share the name “WU CHIH-I”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
TAIWAN SEMICONDUCTOR MFG CO LTD
12 patentsUS11362180B2Jun 14, 2022
Semiconductor device and manufacturing method thereof
TAIWAN SEMICONDUCTOR MFG CO LTD1 citations71
US11232982B2Jan 25, 2022
Deposition system and method using the same
TAIWAN SEMICONDUCTOR MFG CO LTD3 citations69
US9941380B2Apr 10, 2018
Graphene transistor and related methods
TAIWAN SEMICONDUCTOR MFG CO LTD6 citations68
US12518968B2Jan 6, 2026
Integrated circuit device
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations61
US12446279B2Oct 14, 2025
Semiconductor device having 2D channel layer
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations61
US12062540B2Aug 13, 2024
Integrated circuit device and method for forming the same
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations61
US11855150B2Dec 26, 2023
Semiconductor device having 2D channel layer
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations61
US12362170B2Jul 15, 2025
Semiconductor device and method for forming the same
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations58
US12191143B2Jan 7, 2025
Semiconductor device and method for forming the same
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations58
US12376336B2Jul 29, 2025
Semiconductor device with improved source/drain contact and method for forming the same
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations54
US12550337B2Feb 10, 2026
Metal halide resistive memory device and method for forming the same
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations53
US12581676B2Mar 17, 2026
Graphene all around interconnect and manufacturing method thereof
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations52
INTEL CORP
5 patentsUS6605549B2Aug 12, 2003
Method for improving nucleation and adhesion of CVD and ALD films deposited onto low-dielectric-constant dielectrics
INTEL CORP162 citations99
US7122481B2Oct 17, 2006
Sealing porous dielectrics with silane coupling reagents
INTEL CORP15 citations92
US6743712B2Jun 1, 2004
Method of making a semiconductor device by forming a masking layer with a tapered etch profile
INTEL CORP16 citations84
US7456490B2Nov 25, 2008
Sealing porous dielectrics with silane coupling reagents
INTEL CORP9 citations83
US7268075B2Sep 11, 2007
Method to reduce the copper line roughness for increased electrical conductivity of narrow interconnects (<100nm)
INTEL CORP4 citations62