Inventor

LEE TERRY R

US130 patents

⚠️ This page may combine multiple inventors who share the name “LEE TERRY R”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LEE TERRY R

MICRON TECHNOLOGY INC

Reconfigurable memory module and method

Apparatus and methods for a physical layout of simultaneously sub-accessible memory modules

Data transmission circuit for memory subsystem, has switching circuit that selectively connects or disconnects two data bus segments to respectively enable data transmission or I/O circuit connection

Method and system for controlling memory accesses to memory modules having a memory hub architecture

Method of timing calibration using slower data rate pattern

Method and apparatus for bit-to-bit timing correction of a high speed memory bus

Lead frame assemblies with voltage reference plane and IC packages including same

Method and apparatus for collision-free data transfers in a memory device with selectable data or address paths

Memory system that sets a predetermined phase relationship between read and write clock signals at a bus midpoint for a plurality of spaced device locations

Simple output buffer drive strength calibration

Method and apparatus for memory array compressed data testing

Method for performing a split read/write operation in a dynamic random access memory

Timing calibration pattern for SLDRAM

Memory hub and access method having internal prefetch buffers

Wavelength division multiplexed memory module, memory system and method

Apparatus and methods for optically-coupled memory systems

Method and apparatus for synchronous data transfers in a memory device with selectable data or address paths

Semiconductor device with self refresh test mode

Semiconductor device with self refresh test mode

Method and apparatus for bit-to-bit timing correction of a high speed memory bus

Active termination in a multidrop memory system

Method and apparatus for independent output driver calibration

High speed I/O calibration using an input path and simplified logic

Adjustable driver pre-equalization for memory subsystems

Adjustable delay circuit for setting the speed grade of a semiconductor device

Integrated circuit package support system

Adjustable delay circuit for setting the speed grade of a semiconductor device

DRAM compressed data test mode with expected data

Two stage push-pull output buffer circuit with control logic feedback for reducing crossing current, switching noise and the like

Memory hub and access method having internal prefetch buffers

Apparatus and methods for optically-coupled memory systems

Reconfigurable memory module and method

Apparatus and methods for optically-coupled memory systems

Apparatus and methods for optically-coupled memory systems

Dynamic synchronization of data capture on an optical or other high speed communications link

Posted write buffers and methods of posting write requests in memory modules

Wavelength division multiplexed memory module, memory system and method

Semiconductor device with self refresh test mode

Device and system for adjusting delay in a data path based on comparison of data from a latch and data from a register

Method and apparatus for independent output driver calibration

Method and apparatus for synchronous data transfers in a memory device with selectable data or address paths

Method and apparatus for synchronous data transfers in a memory device with selectable data or address paths

Method and apparatus for independent output driver calibration

Method and apparatus for synchronous data transfers in a memory device with selectable data or address paths

Method and apparatus for monitoring component latency drifts

Method and circuit for providing a memory device having hidden row access and row precharge times

Vertical surface mount assembly and methods

KEETH BRENT

Signal delivery in stacked device

ADVANCED MEMORY INTERNATIONAL

Memory system having synchronous-link DRAM (SLDRAM) devices and controller

MICRON TECHNOLOGY LNC

Capacitive multidrop bus compensation