Inventor

DE LESCURE BENOIT

US35 patents

⚠️ This page may combine multiple inventors who share the name “DE LESCURE BENOIT”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

DE LESCURE BENOIT

ARTERIS INC

Editing a NoC topology on top of a floorplan

Synthesis of a network-on-chip (NoC) using performance constraints and objectives

Physically aware topology synthesis of a network

System and method for incremental topology synthesis of a network-on-chip

Editing a NoC topology on top of a floorplan

Constraints and objectives used in synthesis of a network-on-chip (NoC)

System and method for synthesis of a network-on-chip for deadlock-free transformation

Multi-phase topology synthesis of a network-on-chip (NoC)

System and method for generation of quality metrics for optimization tasks in topology synthesis of a network

System and method for isolating faults in a resilient system

Redundancy for cache coherence systems

Synthesis of a network-on-chip (NoC) for insertion of pipeline stages

Incremental topology modification of a network-on-chip

System and method to generate a network-on-chip (NoC) description using incremental topology synthesis

System and method for editing a network-on-chip (NOC)

Constraints and objectives used in synthesis of a network-on-chip (NoC)

Incremental topology modification of a network-on-chip

Quality metrics for optimization tasks in generation of a network

System and method to generate a network-on-chip (NoC) description using incremental topology synthesis

System and method for advanced detection of failures in a network-on-chip

Detection and isolation of faults to prevent propagation of faults in a resilient system

Redundancy for cache coherence systems

System and method for transaction broadcast in a network on chip

Broadcast adapters in a network-on-chip

System and method for transaction broadcast in a network on chip

System and method for logic functional redundancy

Switch with virtual channels for soft locking in a network-on-chip (NoC)

System and method for using soft lock with virtual channels in a network-on-chip (NoC)

Automatic configuration of pipeline modules in an electronics system

System and method for performing transaction aggregation in a network-on-chip (NoC)

System and method for deadlock detection in network-on-chip (NoC) having external dependencies

System and method for generating and using physical roadmaps in network synthesis

System and method for synthesis of connectivity to an interconnect in a multi-protocol system-on-chip (SoC)

DE LESCURE BENOIT

Apparatus and methods for on layer concurrency in an integrated circuit

BRINKS RAY

Intelligent power controller