Inventor

KOBRINSKY MAURO J

US75 patents

⚠️ This page may combine multiple inventors who share the name “KOBRINSKY MAURO J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KOBRINSKY MAURO J

INTEL CORP

Thinning techniques for wafer-to-wafer vertical stacks

Metal-insulator-metal capacitor formation techniques

Wafer bonding with highly compliant plate having filler material enclosed hollow core

Integrated circuit device with back-side interconnection to deep source/drain semiconductor

Methods of forming backside self-aligned vias and structures formed thereby

Method and structure for interfacing electronic devices

Gate-all-around integrated circuit structures having asymmetric source and drain contact structures

Transistors with back-side contacts to create three dimensional memory and logic

Three-dimensional nanoribbon-based dynamic random-access memory

Three-dimensional nanoribbon-based static random-access memory

Backside contact resistance reduction for semiconductor devices with metallization on both sides

Thin film transistor based memory cells on both sides of a layer of logic devices

Dense memory arrays utilizing access transistors with back-side contacts

Integrated circuit device with crenellated metal trace layout

Methods of forming backside self-aligned vias and structures formed thereby

Optical I/O system using planar light-wave integrated circuit

Three-dimensional stacked substrate arrangements

Gate-all-around integrated circuit structures having asymmetric source and drain contact structures

Integrated circuit device with back-side interconnection to deep source/drain semiconductor

Deep trench via for three-dimensional integrated circuit

Three-dimensional memory arrays with layer selector transistors

Backside source/drain replacement for semiconductor devices with metallization on both sides

Structure and method to self align via to top and bottom of tight pitch metal interconnect layers

Microelectronic conductive routes and methods of making the same

Integrated circuit assemblies with direct chip attach to circuit boards

Metal-insulator-metal capacitor formation techniques

Differential planarization

Interconnect fabricated with flowable copper

Integrated circuit structures having partitioned source or drain contact structures

Integrated circuit structures having differentiated neighboring partitioned source or drain contact structures

Fluid viscosity control during wafer bonding

Wafer to wafer bonding with low wafer distortion

Techniques for enhancing fracture resistance of interconnects

Vertically stacked and bonded memory arrays

Gate-all-around integrated circuit structures having asymmetric source and drain contact structures

Hybrid manufacturing for integrating photonic and electronic components

Method of forming self-passivating interconnects and resulting devices

Integrated circuit structures having conductive structures in fin isolation regions

Device layer interconnects

Integrated circuit structures having backside gate tie-down

Hybrid manufacturing for integrated circuit devices and assemblies

Three-dimensional memory arrays with layer selector transistors

Deep trench via for three-dimensional integrated circuit

Three-dimensional nanoribbon-based dynamic random-access memory

Integrated circuit device with crenellated metal trace layout

KOBRINSKY MAURO J

Optical I/O system using planar light-wave integrated circuit

Fabrication of planar light-wave circuits (PLCS) for optical I/O

Optical waveguide structure

RAMANATHAN SHRIRAM

Three-dimensional stacked substrate arrangements

TSENG JIA-HUNG

Waveguide integration on laser for alignment-tolerant assembly