Inventor

SHUKLA SUNIL K

US19 patents

⚠️ This page may combine multiple inventors who share the name “SHUKLA SUNIL K”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SHUKLA SUNIL K

IBM

Tightly coupled processor arrays using coarse grained reconfigurable architecture with iteration level commits

Loop management in multi-processor dataflow architecture

Communication stack for software-hardware co-execution on heterogeneous computing systems with processors and reconfigurable logic (FPGAs)

Sparse systolic array design

Tightly coupled processor arrays using coarse grained reconfigurable architecture with iteration level commits

Cycle-accurate replay and debugging of running FPGA systems

Padding input data for artificial intelligence accelerators

Programmable data delivery by load and store agents on a processing chip interfacing with on-chip memory components and directing data to external memory components

Cycle-accurate replay and debugging of running FPGA systems

Single function to perform combined matrix multiplication and bias add operations

Instruction initialization in a dataflow architecture

Parallel garbage collection implemented in hardware

Parallel garbage collection implemented in hardware

Parallel garbage collection implemented in hardware

Communication stack for software-hardware co-execution on heterogeneous computing systems with processors and reconfigurable logic (FPGAs)

Exploiting fine-grained structured weight sparsity in systolic arrays

Programmable multicast protocol for ring-topology based artificial intelligence systems

BACON DAVID F

Garbage collection implemented in hardware

SHUKLA SUNIL K

Best clock frequency search for FPGA-based design