Inventor
KIM JINGWAN
KR17 patents
⚠️ This page may combine multiple inventors who share the name “KIM JINGWAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
STATS CHIPPAC LTD
8 patentsUS8836114B2Sep 16, 2014
Semiconductor device and method of forming Fo-WLCSP having conductive layers and conductive vias separated by polymer layers
STATS CHIPPAC LTD15 citations92
US8343810B2Jan 1, 2013
Semiconductor device and method of forming Fo-WLCSP having conductive layers and conductive vias separated by polymer layers
STATS CHIPPAC LTD18 citations92
US8003496B2Aug 23, 2011
Semiconductor device and method of mounting semiconductor die to heat spreader on temporary carrier and forming polymer layer and conductive layer over the die
STATS CHIPPAC LTD22 citations92
US8004093B2Aug 23, 2011
Integrated circuit package stacking system
STATS CHIPPAC LTD37 citations91
US9401347B2Jul 26, 2016
Semiconductor device and method of forming a shielding layer over a semiconductor die disposed in a cavity of an interconnect structure and grounded through the die TSV
STATS CHIPPAC LTD5 citations83
US8932908B2Jan 13, 2015
Semiconductor device and method of forming partially-etched conductive layer recessed within substrate for bonding to semiconductor die
STATS CHIPPAC LTD5 citations82
US9379064B2Jun 28, 2016
Semiconductor device and method of mounting semiconductor die to heat spreader on temporary carrier and forming polymer layer and conductive layer over the die
STATS CHIPPAC LTD4 citations72
US8937371B2Jan 20, 2015
Semiconductor device and method of forming a shielding layer over a semiconductor die disposed in a cavity of an interconnect structure and grounded through the die TSV
STATS CHIPPAC LTD2 citations62
KIM JINGWAN
3 patentsUS8432028B2Apr 30, 2013
Integrated circuit packaging system with package-on-package and method of manufacture thereof
KIM JINGWAN8 citations78
US8310038B2Nov 13, 2012
Integrated circuit packaging system with embedded conductive structure and method of manufacture thereof
KIM JINGWAN2 citations59
US8476135B2Jul 2, 2013
Integrated circuit packaging system with vertical interconnects and method of manufacture thereof
KIM JINGWAN1 citations46
STATS CHIPPAC PTE LTD
2 patentsLEE KYUWON
2 patentsUS8288202B2Oct 16, 2012
Method of forming partially-etched conductive layer recessed within substrate for bonding to semiconductor die
LEE KYUWON2 citations57
US8502392B2Aug 6, 2013
Semiconductor device with partially-etched conductive layer recessed within substrate for bonding to semiconductor die
LEE KYUWON0 citations46