Inventor

HALLIYAL ARVIND

US82 patents

⚠️ This page may combine multiple inventors who share the name “HALLIYAL ARVIND”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HALLIYAL ARVIND

ADVANCED MICRO DEVICES INC

Use of high-K dielectric material in modified ONO structure for semiconductor devices

Use of high-k dielectric materials in modified ONO structure for semiconductor devices

Preparation of composite high-K/standard-K dielectrics for semiconductor devices

Use of high-K dielectric material in modified ONO structure for semiconductor devices

Integrated process for fabrication of graded composite dielectric material layers for semiconductor devices

Process for reducing hydrogen contamination in dielectric materials in memory devices

Semiconductor memory with deuterated materials

Non-reducing process for deposition of polysilicon gate electrode over high-K gate dielectric material

Process for fabricating an ONO structure having a silicon-rich silicon nitride layer

High temperature oxide deposition process for fabricating an ONO floating-gate electrode in a two bit EEPROM device

Gate array with multiple dielectric properties and method for forming same

Method of fabricating an ONO dielectric by nitridation for MNOS memory cells

Scatterometry and acoustic based active control of thin film deposition process

Laser thermal annealing methods for flash memory devices

Implant damage removal by laser thermal annealing

System and method for active control of BPSG deposition

Laser thermal annealing method for high dielectric constant gate oxide films

Interlayer dielectric void detection

Acoustic microbalance for in-situ deposition process monitoring and control

Precision high-K intergate dielectric layer

Doped copper interconnects using laser thermal annealing

Interfacial barrier layer in semiconductor devices with high-K gate dielectric material

Replacing layers of an intergate dielectric layer with high-K material for improved scalability

Integrated process for depositing layer of high-K dielectric with in-situ control of K value and thickness of high-K dielectric layer

X-ray reflectance system to determine suitability of SiON ARC layer

Process integration of electrical thickness measurement of gate oxide and tunnel oxides by corona discharge technique

In-situ thickness measurement for use in semiconductor processing

Silicon-starved PECVD method for metal gate electrode dielectric spacer

Nitridation process for fabricating an ONO floating-gate electrode in a two-bit EEPROM device

Preparation of composite high-K/standard-K dielectrics for semiconductor devices

UV-blocking layer for reducing UV-induced charging of SONOS dual-bit flash memory devices in BEOL

Spacers with a graded dielectric constant for semiconductor devices having a high-K dielectric

Method of forming reliable Cu interconnects

Memory manufacturing process using bitline rapid thermal anneal

Memory wordline hard mask

Flash memory having pre-interpoly dielectric treatment layer and method of forming

Process for optimizing pocket implant profile by RTA implant annealing for a non-volatile semiconductor device

Method to generate a MONOS type flash cell using polycrystalline silicon as an ONO top layer

Process for fabricating an ONO floating-gate electrode in a two-bit EEPROM device using rapid-thermal-chemical-vapor-deposition

FASL LLC

ONO fabrication process for increasing oxygen content at bottom oxide-substrate interface in flash memory devices

ONO fabrication process for reducing oxygen vacancy content in bottom oxide layer in flash memory devices

Method of formation of semiconductor resistant to hot carrier injection stress

Process for fabrication of nitride layer with reduced hydrogen content in ONO structure in semiconductor device

ONO fabrication process for reducing oxygen vacancy content in bottom oxide layer in flash memory devices

Flash memory device and method of fabrication thereof including a bottom oxide layer with two regions with different concentrations of nitrogen

Process for fabrication of spacer layer with reduced hydrogen content in semiconductor device

Method of manufacturing a semiconductor memory with deuterated materials

SPANSION LLC

Integrated ONO processing for semiconductor devices using in-situ steam generation (ISSG) process

Method of formation of gate stack spacer and charge storage materials having reduced hydrogen content in charge trapping dielectric flash memory device

HAUN MICHAEL J

Partially crystallizable glass compositions