Inventor

EN WILLIAM G

US52 patents

⚠️ This page may combine multiple inventors who share the name “EN WILLIAM G”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

EN WILLIAM G

ADVANCED MICRO DEVICES INC

Method and apparatus for controlling the thickness of a selective epitaxial growth layer

Implantation into high-K dielectric material after gate etch to facilitate removal

Field effect transistor with self alligned double gate and method of forming same

SOI MOSFET and method of fabrication

Method of fabricating a silicon-on-insulator (SOI) chip having an active layer of non-uniform thickness

Silicon-on-insulator (SOI) chip having an active layer of non-uniform thickness

Method of fabrication of semiconductor-on-insulator (SOI) wafer having a Si/SiGe/Si active layer

Gate array with multiple dielectric properties and method for forming same

CMOS inverter configured from double gate MOSFET and method of fabricating same

SOI device with structure for enhancing carrier recombination and method of fabricating same

Method to reduce parasitic capacitance of MOS transistors

Method of forming a semiconductor device

Method for reducing gate oxide surface irregularities

SOI MOSFET having amorphized source drain and method of fabrication

Interfacial barrier layer in semiconductor devices with high-K gate dielectric material

Multi-Thickness silicide device formed by succesive spacers

Method of making a multi-thickness silicide SOI device

Local interconnects for improved alignment tolerance and size reduction

Protection of hydrogen sensitive regions in semiconductor devices from the positive charge associated with plasma deposited barriers or layers

Enhanced silicidation of polysilicon gate electrodes

Semiconductor-on-insulator (SOI) wafer having a Si/SiGe/Si active layer and method of fabrication using wafer bonding

SOI device with different silicon thicknesses

Multipurpose cap layer dielectric

Methods for in-situ removal of an anti-reflective coating during an oxide resistor protect etching process

Methods and arrangements for determining an endpoint for an in-situ local interconnect etching process

Silicon oxime spacer for preventing over-etching during local interconnect formation

Method of forming a semiconductor device

Method of fabricating multi-thickness silicide device formed by disposable spacers

SOI device with structure for enhancing carrier recombination and method of fabricating same

Array of gate dielectric structures to measure gate dielectric thickness and parasitic capacitance

Formation of a barrier layer for tungsten damascene interconnects by nitrogen implantation of amorphous silicon or polysilicon

Treatment of dielectric material to enhance etch rate

Method and circuit for measuring charge dump of an individual transistor in an SOI device

Methods and arrangements for insulating local interconnects for improved alignment tolerance and size reduction

Methods and arrangements for determining an endpoint for an in-situ local interconnect etching process

In-situ etch of multiple layers during formation of local interconnects

Methods and arrangements for improved spacer formation within a semiconductor device

Method for manufacturing a semiconductor device with self-aligned protection diode

Semiconductor device with self-aligned protection diode

Methods for preventing deleterious punch-through during local interconnect formation

Nitride offset spacer to minimize silicon recess by using poly reoxidation layer as etch stop layer

Device and method for testing performance of silicon structures

Methods for removal of an anti-reflective coating following a resist protect etching process

Methods for in-situ removal of an anti-reflective coating during a nitride resistor protect etching process

Array of gate dielectric structures to measure gate dielectric thickness and parasitic capacitance

SILICON GENESIS CORP

Cleaving process to fabricate multilayered substrates using low implantation doses

Method for fabricating multi-layered substrates

Cleaving process to fabricate multilayered substrates using low implantation doses

High temperature implant apparatus

Cleaving process to fabricate multilayered substrates using low implantation doses