Inventor

NARIANI SUBHASH R

US20 patents

Patents

20 patents

US5587332ADec 24, 1996

Method of making flash memory cell

VLSI TECHNOLOGY INC72 citations96

US5493146AFeb 20, 1996

Anti-fuse structure for reducing contamination of the anti-fuse material

VLSI TECHNOLOGY INC77 citations96

US5290734AMar 1, 1994

Method for making anti-fuse structures

VLSI TECHNOLOGY INC78 citations95

US5120679AJun 9, 1992

Anti-fuse structures and methods for making same

VLSI TECHNOLOGY INC116 citations95

US5638006AJun 10, 1997

Method and apparatus for wafer level prediction of thin oxide reliability using differentially sized gate-like antennae

VLSI TECHNOLOGY INC20 citations92

US5573970ANov 12, 1996

Method for reducing contamination of anti-fuse material in an anti-fuse structure

VLSI TECHNOLOGY INC19 citations92

US5548224AAug 20, 1996

Method and apparatus for wafer level prediction of thin oxide reliability

VLSI TECHNOLOGY INC21 citations92

US5470775ANov 28, 1995

Method of forming a polysilicon-on-silicide capacitor

VLSI TECHNOLOGY INC32 citations92

US5328865AJul 12, 1994

Method for making cusp-free anti-fuse structures

VLSI TECHNOLOGY INC35 citations92

US5128279AJul 7, 1992

Charge neutralization using silicon-enriched oxide layer

VLSI TECHNOLOGY INC30 citations92

US5057897AOct 15, 1991

Charge neutralization using silicon-enriched oxide layer

VLSI TECHNOLOGY INC49 citations92

USRE36893EOct 3, 2000

Anti-fuse structure for reducing contamination of the anti-fuse material

VLSI TECHNOLOGY INC7 citations74

US5763937AJun 9, 1998

Device reliability of MOS devices using silicon rich plasma oxide films

VLSI TECHNOLOGY INC16 citations74

US5602056AFeb 11, 1997

Method for forming reliable MOS devices using silicon rich plasma oxide film

VLSI TECHNOLOGY INC12 citations74

US5374833ADec 20, 1994

Structure for suppression of field inversion caused by charge build-up in the dielectric

VLSI TECHNOLOGY INC7 citations74

US5218511AJun 8, 1993

Inter-silicide capacitor

VLSI TECHNOLOGY INC11 citations74

US5198381AMar 30, 1993

Method of making an E2 PROM cell with improved tunneling properties having two implant stages

VLSI TECHNOLOGY INC6 citations74

US6015732AJan 18, 2000

Dual gate oxide process with increased reliability

VLSI TECHNOLOGY INC10 citations69

US5492865AFeb 20, 1996

Method of making structure for suppression of field inversion caused by charge build-up in the dielectric

VLSI TECHNOLOGY INC2 citations63

US5371393ADec 6, 1994

EEPROM cell with improved tunneling properties

VLSI TECHNOLOGY INC4 citations63