Inventor

IBOK EFFIONG

US44 patents

Patents

44 patents

US6451641B1Sep 17, 2002

Non-reducing process for deposition of polysilicon gate electrode over high-K gate dielectric material

ADVANCED MICRO DEVICES INC148 citations98

US6329256B1Dec 11, 2001

Self-aligned damascene gate formation with low gate resistance

ADVANCED MICRO DEVICES INC102 citations98

US6037671AMar 14, 2000

Stepper alignment mark structure for maintaining alignment integrity

ADVANCED MICRO DEVICES INC107 citations98

US6630383B1Oct 7, 2003

Bi-layer floating gate for improved work function between floating gate and a high-K dielectric layer

ADVANCED MICRO DEVICES INC74 citations96

US6444555B2Sep 3, 2002

Method for establishing ultra-thin gate insulator using anneal in ammonia

ADVANCED MICRO DEVICES INC60 citations96

US6171962B1Jan 9, 2001

Shallow trench isolation formation without planarization mask

ADVANCED MICRO DEVICES INC68 citations96

US6025228AFeb 15, 2000

Method of fabricating an oxynitride-capped high dielectric constant interpolysilicon dielectric structure for a low voltage non-volatile memory

ADVANCED MICRO DEVICES INC79 citations96

US5930645AJul 27, 1999

Shallow trench isolation formation with reduced polish stop thickness

ADVANCED MICRO DEVICES INC87 citations96

US6693004B1Feb 17, 2004

Interfacial barrier layer in semiconductor devices with high-K gate dielectric material

ADVANCED MICRO DEVICES INC33 citations93

US6599810B1Jul 29, 2003

Method of fabricating a high dielectric constant interpolysilicon dielectric structure for a low voltage non-volatile memory

ADVANCED MICRO DEVICES INC26 citations93

US5940718AAug 17, 1999

Nitridation assisted polysilicon sidewall protection in self-aligned shallow trench isolation

ADVANCED MICRO DEVICES INC33 citations93

US6735123B1May 11, 2004

High density dual bit flash memory cell with non planar structure

ADVANCED MICRO DEVICES INC20 citations92

US6429083B1Aug 6, 2002

Removable spacer technology using ion implantation to augment etch rate differences of spacer materials

ADVANCED MICRO DEVICES INC32 citations92

US6034395AMar 7, 2000

Semiconductor device having a reduced height floating gate

ADVANCED MICRO DEVICES INC21 citations92

US6472233B1Oct 29, 2002

MOSFET test structure for capacitance-voltage measurements

ADVANCED MICRO DEVICES INC45 citations91

US6472283B1Oct 29, 2002

MOS transistor processing utilizing UV-nitride removable spacer and HF etch

ADVANCED MICRO DEVICES INC51 citations91

US6344396B1Feb 5, 2002

Removable spacer technology using ion implantation for forming asymmetric MOS transistors

ADVANCED MICRO DEVICES INC51 citations91

US6239031B1May 29, 2001

Stepper alignment mark structure for maintaining alignment integrity

ADVANCED MICRO DEVICES INC39 citations91

US5879975AMar 9, 1999

Heat treating nitrogen implanted gate electrode layer for improved gate electrode etch profile

ADVANCED MICRO DEVICES INC33 citations91

US6342423B1Jan 29, 2002

MOS-type transistor processing utilizing UV-nitride removable spacer and HF etch

ADVANCED MICRO DEVICES INC16 citations84

US6225170B1May 1, 2001

Self-aligned damascene gate with contact formation

ADVANCED MICRO DEVICES INC19 citations84

US5970363AOct 19, 1999

Shallow trench isolation formation with improved trench edge oxide

ADVANCED MICRO DEVICES INC19 citations84

US5970362AOct 19, 1999

Simplified shallow trench isolation formation with no polish stop

ADVANCED MICRO DEVICES INC17 citations84

US6593637B1Jul 15, 2003

Method for establishing component isolation regions in SOI semiconductor device

ADVANCED MICRO DEVICES INC11 citations74

US6380047B1Apr 30, 2002

Shallow trench isolation formation with two source/drain masks and simplified planarization mask

ADVANCED MICRO DEVICES INC9 citations74

US6372582B1Apr 16, 2002

Indium retrograde channel doping for improved gate oxide reliability

ADVANCED MICRO DEVICES INC13 citations74

US6235607B1May 22, 2001

Method for establishing component isolation regions in SOI semiconductor device

ADVANCED MICRO DEVICES INC13 citations74

US6207542B1Mar 27, 2001

Method for establishing ultra-thin gate insulator using oxidized nitride film

ADVANCED MICRO DEVICES INC14 citations74

US6800568B1Oct 5, 2004

Methods for the deposition of high-K films and high-K films produced thereby

ADVANCED MICRO DEVICES INC2 citations63

US6762454B1Jul 13, 2004

Stacked polysilicon layer for boron penetration inhibition

ADVANCED MICRO DEVICES INC4 citations63

US6417041B1Jul 9, 2002

Method for fabricating high permitivity dielectric stacks having low buffer oxide

ADVANCED MICRO DEVICES INC5 citations63

US6399519B1Jun 4, 2002

Method for establishing ultra-thin gate insulator having annealed oxide and oxidized nitride

ADVANCED MICRO DEVICES INC5 citations63

US6162699ADec 19, 2000

Method for generating limited isolation trench width structures and a device having a narrow isolation trench surrounding its periphery

ADVANCED MICRO DEVICES INC2 citations63

US6153486ANov 28, 2000

Method for establishing shallow junction in semiconductor device to minimize junction capacitance

ADVANCED MICRO DEVICES INC6 citations63

US6177312B1Jan 23, 2001

Method for removing contaminate nitrogen from the peripheral gate region of a non-volatile memory device during production of such device

ADVANCED MICRO DEVICES INC5 citations62

US6090713AJul 18, 2000

Shallow trench isolation formation with simplified reverse planarization mask

ADVANCED MICRO DEVICES INC5 citations60

US6229198B1May 8, 2001

Non-uniform gate doping for reduced overlap capacitance

ADVANCED MICRO DEVICES INC6 citations59

US6204157B1Mar 20, 2001

Method for establishing shallow junction in semiconductor device to minimize junction capacitance

ADVANCED MICRO DEVICES INC0 citations52

US6165877ADec 26, 2000

Method for establishing shallow junction in semiconductor device to minimize junction capacitance

ADVANCED MICRO DEVICES INC0 citations52

IBOK EFFIONG

Patents

Non-reducing process for deposition of polysilicon gate electrode over high-K gate dielectric material

Self-aligned damascene gate formation with low gate resistance

Stepper alignment mark structure for maintaining alignment integrity

Bi-layer floating gate for improved work function between floating gate and a high-K dielectric layer

Method for establishing ultra-thin gate insulator using anneal in ammonia

Shallow trench isolation formation without planarization mask

Method of fabricating an oxynitride-capped high dielectric constant interpolysilicon dielectric structure for a low voltage non-volatile memory

Shallow trench isolation formation with reduced polish stop thickness

Interfacial barrier layer in semiconductor devices with high-K gate dielectric material

Shallow trench isolation formation with ion implantation

Shallow trench isolation formation with spacer-assisted ion implantation

Shallow trench isolation with spacers for improved gate oxide quality

Shallow trench isolation formation with simplified reverse planarization mask

Shallow trench isolation formation with trench wall spacer

Method of fabricating a high dielectric constant interpolysilicon dielectric structure for a low voltage non-volatile memory

Nitridation assisted polysilicon sidewall protection in self-aligned shallow trench isolation

High density dual bit flash memory cell with non planar structure

Removable spacer technology using ion implantation to augment etch rate differences of spacer materials

Semiconductor device having a reduced height floating gate

MOSFET test structure for capacitance-voltage measurements

MOS transistor processing utilizing UV-nitride removable spacer and HF etch

Removable spacer technology using ion implantation for forming asymmetric MOS transistors

Stepper alignment mark structure for maintaining alignment integrity

Heat treating nitrogen implanted gate electrode layer for improved gate electrode etch profile

MOS-type transistor processing utilizing UV-nitride removable spacer and HF etch

Self-aligned damascene gate with contact formation

Shallow trench isolation formation with improved trench edge oxide

Simplified shallow trench isolation formation with no polish stop

Method for establishing component isolation regions in SOI semiconductor device

Shallow trench isolation formation with two source/drain masks and simplified planarization mask

Indium retrograde channel doping for improved gate oxide reliability

Method for establishing component isolation regions in SOI semiconductor device

Method for establishing ultra-thin gate insulator using oxidized nitride film

Methods for the deposition of high-K films and high-K films produced thereby

Stacked polysilicon layer for boron penetration inhibition

Method for fabricating high permitivity dielectric stacks having low buffer oxide

Method for establishing ultra-thin gate insulator having annealed oxide and oxidized nitride

Method for generating limited isolation trench width structures and a device having a narrow isolation trench surrounding its periphery

Method for establishing shallow junction in semiconductor device to minimize junction capacitance

Method for removing contaminate nitrogen from the peripheral gate region of a non-volatile memory device during production of such device

Shallow trench isolation formation with simplified reverse planarization mask

Non-uniform gate doping for reduced overlap capacitance

Method for establishing shallow junction in semiconductor device to minimize junction capacitance

Method for establishing shallow junction in semiconductor device to minimize junction capacitance