Inventor
SANKAR NARENDRA
US26 patents
⚠️ This page may combine multiple inventors who share the name “SANKAR NARENDRA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
MIPS TECH INC
16 patentsUS7020879B1Mar 28, 2006
Interrupt and exception handling for multi-streaming digital processors
MIPS TECH INC143 citations98
US7032226B1Apr 18, 2006
Methods and apparatus for managing a buffer of events in the background
MIPS TECH INC69 citations97
US6789100B2Sep 7, 2004
Interstream control and communications for multi-streaming digital processors
MIPS TECH INC80 citations97
US7139898B1Nov 21, 2006
Fetch and dispatch disassociation apparatus for multistreaming processors
MIPS TECH INC44 citations96
US7900207B2Mar 1, 2011
Interrupt and exception handling for multi-streaming digital processors
MIPS TECH INC15 citations92
US7502876B1Mar 10, 2009
Background memory manager that determines if data structures fits in memory with memory state transactions map
MIPS TECH INC49 citations92
US7467385B2Dec 16, 2008
Interrupt and exception handling for multi-streaming digital processors
MIPS TECH INC20 citations92
US7058064B2Jun 6, 2006
Queueing system for processors in packet routing operations
MIPS TECH INC23 citations92
US7529907B2May 5, 2009
Method and apparatus for improved computer load and store operations
MIPS TECH INC12 citations84
US7715410B2May 11, 2010
Queueing system for processors in packet routing operations
MIPS TECH INC6 citations73
US7661112B2Feb 9, 2010
Methods and apparatus for managing a buffer of events in the background
MIPS TECH INC5 citations73
US7636836B2Dec 22, 2009
Fetch and dispatch disassociation apparatus for multistreaming processors
MIPS TECH INC1 citations63
US7406586B2Jul 29, 2008
Fetch and dispatch disassociation apparatus for multi-streaming processors
MIPS TECH INC4 citations63
US7926062B2Apr 12, 2011
Interrupt and exception handling for multi-streaming digital processors
MIPS TECH INC3 citations62
US7765546B2Jul 27, 2010
Interstream control and communications for multi-streaming digital processors
MIPS TECH INC2 citations62
US7551626B2Jun 23, 2009
Queueing system for processors in packet routing operations
MIPS TECH INC4 citations62
NAT SEMICONDUCTOR CORP
5 patentsUS5699506ADec 16, 1997
Method and apparatus for fault testing a pipelined processor
NAT SEMICONDUCTOR CORP33 citations92
US5752273AMay 12, 1998
Apparatus and method for efficiently determining addresses for misaligned data stored in memory
NAT SEMICONDUCTOR CORP27 citations91
US5692146ANov 25, 1997
Method of implementing fast 486TM microprocessor compatible string operations
NAT SEMICONDUCTOR CORP24 citations91
US5546353AAug 13, 1996
Partitioned decode circuit for low power operation
NAT SEMICONDUCTOR CORP11 citations74
US5815736ASep 29, 1998
Area and time efficient extraction circuit
NAT SEMICONDUCTOR CORP0 citations42
CLEARWATER NETWORKS INC
3 patentsUS6477562B2Nov 5, 2002
Prioritized instruction scheduling for multi-streaming processors
CLEARWATER NETWORKS INC184 citations98
US6389449B1May 14, 2002
Interstream control and communications for multi-streaming digital processors
CLEARWATER NETWORKS INC171 citations98
US6292888B1Sep 18, 2001
Register transfer unit for electronic processor
CLEARWATER NETWORKS INC112 citations97