Inventor
DEHERRERA MARK
US12 patents
⚠️ This page may combine multiple inventors who share the name “DEHERRERA MARK”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
FREESCALE SEMICONDUCTOR INC
5 patentsUS6835423B2Dec 28, 2004
Method of fabricating a magnetic element with insulating veils
FREESCALE SEMICONDUCTOR INC141 citations98
US6784510B1Aug 31, 2004
Magnetoresistive random access memory device structures
FREESCALE SEMICONDUCTOR INC44 citations96
US6890770B2May 10, 2005
Magnetoresistive random access memory device structures and methods for fabricating the same
FREESCALE SEMICONDUCTOR INC10 citations73
US7333360B2Feb 19, 2008
Apparatus for pulse testing a MRAM device and method therefore
FREESCALE SEMICONDUCTOR INC3 citations62
US6912107B2Jun 28, 2005
Magnetic element with insulating veils and fabricating method thereof
FREESCALE SEMICONDUCTOR INC4 citations62
MOTOROLA INC
4 patentsUS6331943B1Dec 18, 2001
MTJ MRAM series-parallel architecture
MOTOROLA INC300 citations98
US6233172B1May 15, 2001
Magnetic element with dual magnetic states and fabrication method thereof
MOTOROLA INC205 citations98
US6365419B1Apr 2, 2002
High density MRAM cell array
MOTOROLA INC101 citations97
US6544801B1Apr 8, 2003
Method of fabricating thermally stable MTJ cell and apparatus
MOTOROLA INC99 citations96
EVERSPIN TECHNOLOGIES INC
3 patentsUS9543041B2Jan 10, 2017
Configuration and testing for magnetoresistive memory to ensure long term continuous operation
EVERSPIN TECHNOLOGIES INC4 citations73
US10923170B2Feb 16, 2021
Determining bias configuration for write operations in memory to improve device performance during normal operation as well as to improve the effectiveness of testing routines
EVERSPIN TECHNOLOGIES INC0 citations62
US10262713B2Apr 16, 2019
Determining bias configuration for write operations in memory to improve device performance during normal operation as well as to improve the effectiveness of testing routines
EVERSPIN TECHNOLOGIES INC0 citations52