Inventor

OOWAKI YUKIHITO

JP78 patents

⚠️ This page may combine multiple inventors who share the name “OOWAKI YUKIHITO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

OOWAKI YUKIHITO

TOSHIBA KK

MISFET semiconductor device having relative impurity concentration levels between layers

Semiconductor device

Ferroelectric memory

Ferroelectric memory device

Chain type ferroelectric memory with isolation transistors coupled between a sense amplifier and an equalization circuit

MIS transistor having a large driving current and method for producing the same

Semiconductor memory device such as a DRAM capable of holding data without refresh

Dynamic random access memory device with the combined open/folded bit-line pair arrangement

Random access memory with divided memory banks and data read/write architecture therefor

Integrated semiconductor memory with internal voltage booster of lesser dependency on power supply voltage

MOS type random access memory with interference noise eliminator

Processor and information processing apparatus with a reconfigurable circuit

Ferroelectric memory having a device responsive to current lowering

Ferroelectric memory having memory cell array accessibility safeguards

Dynamic semiconductor memory device having an improved sense amplifier layout arrangement

MOS semiconductor device with memory cells each having storage capacitor and transfer transistor

NAND-type dynamic RAM having temporary storage register and sense amplifier coupled to multi-open bit lines

Dynamic semiconductor memory device having an improved sense amplifier layout arrangement

Semiconductor memory device having folded bit line array and an open bit line array with imbalance correction

NAND-type dynamic RAM having temporary storage register and sense amplifier coupled to multi-open bit lines

Semiconductor memory

Dynamic random access memory with enhanced sense-amplifier circuit

Dynamic semiconductor memory device with twisted bit-line structure

Dynamic type semiconductor memory device

Configurable integrated circuit and method of testing the same

Dynamic random access memory device

Semiconductor memory device

Clock converting circuit

Method of manufacturing a semiconductor device by detachably mounting substrates to a holder board

Integrated circuit with stacked sub-circuits between Vcc and ground so as to conserve power and reduce the voltage across any one transistor

Semiconductor memory device using dynamic type memory cells

Semiconductor memory device with reduced read time and power consumption

Integrated semiconductor memory with internal voltage booster of lesser dependency on power supply voltage

Semiconductor integrated circuit device

Dynamic random access memory with variable sense-amplifier drive capacity

Semiconductor device adapted to minimize clock skew

Semiconductor memory device

Apparatus comprising clock control circuit and device using internal clock signal synchronized to external clock signal

Semiconductor memory device using ferroelectric film

Semiconductor memory device having a multilayered bitline structure with respective wiring layers for reading and writing data

Semiconductor memory device in which a failed memory cell is placed with another memory cell

Ferroelectric random access memory with isolation transistors coupled between a sense amplifier and an equalization circuit

Ferroelectric random access memory

Method of manufacturing semiconductor memory device

Semiconductor memory device

Dynamic semiconductor memory device having an improved sense amplifier layout arrangement

MOS semiconductor device with memory cells each having storage capacitor and transfer transistor

MIS transistor and method for producing same

TOSHIBA CORP

Semiconductor integrated circuit

Semiconductor integrated circuit having suppressed leakage currents