P

Inventor

WALTON JOHN K

US48 patents
⚠️ This page may combine multiple inventors who share the name “WALTON JOHN K”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

EMC CORP

46 patents
US6973551B1Dec 6, 2005

Data storage system having atomic memory operation

EMC CORP67 citations98
US6886116B1Apr 26, 2005

Data storage system adapted to validate error detection logic used in such system

EMC CORP67 citations98
US6779150B1Aug 17, 2004

CRC error detection system and method

EMC CORP82 citations98
US6904556B2Jun 7, 2005

Systems and methods which utilize parity sets

EMC CORP63 citations96
US6636933B1Oct 21, 2003

Data storage system having crossbar switch with multi-staged routing

EMC CORP63 citations96
US6389494B1May 14, 2002

System for interfacing a data storage system to a host utilizing a plurality of busses for carrying end-user data and a separate bus for carrying interface state data

EMC CORP77 citations96
US6687797B1Feb 3, 2004

Arbitration system and method

EMC CORP21 citations93
US6578126B1Jun 10, 2003

Memory system and method of using same

EMC CORP46 citations93
US6195770B1Feb 27, 2001

Data storage system

EMC CORP29 citations93
US5953265ASep 14, 1999

Memory having error detection and correction

EMC CORP25 citations93
US5943287AAug 24, 1999

Fault tolerant memory system

EMC CORP30 citations93
US5936844AAug 10, 1999

Memory system printed circuit board

EMC CORP19 citations93
US7552282B1Jun 23, 2009

Method, computer readable medium, and data storage system for selective data replication of cached data

EMC CORP35 citations92
US6910145B2Jun 21, 2005

Data transmission across asynchronous clock domains

EMC CORP45 citations92
US6347365B1Feb 12, 2002

Data storage system having a[n] memory responsive to clock pulses produced on a bus and clock pulses produced by an internal clock

EMC CORP41 citations92
US5822777AOct 13, 1998

Dual bus data storage system having an addressable memory with timer controller fault detection of data transfer between the memory and the buses

EMC CORP32 citations92
US7774631B1Aug 10, 2010

Method and system for minimizing power consumption in a multiprocessor data storage system

EMC CORP19 citations84
US7124245B1Oct 17, 2006

Data storage system having cache memory manager with packet switching network

EMC CORP14 citations84
US7020754B1Mar 28, 2006

Method and system for maintaining data integrity using dual write operations

EMC CORP15 citations84
US6882620B1Apr 19, 2005

Token exchange system with fault protection

EMC CORP12 citations84
US6505321B1Jan 7, 2003

Fault tolerant parity generation

EMC CORP15 citations84
US6397281B1May 28, 2002

Bus arbitration system

EMC CORP16 citations84
US6145042ANov 7, 2000

Timing protocol for a data storage system

EMC CORP19 citations84
US7010740B1Mar 7, 2006

Data storage system having no-operation command

EMC CORP10 citations74
US6868516B1Mar 15, 2005

Method for validating write data to a memory

EMC CORP11 citations74
US6609185B1Aug 19, 2003

Data storage system having majority gate filter

EMC CORP9 citations74
US6604176B1Aug 5, 2003

Data storage system having plural fault domains

EMC CORP11 citations74
US6594739B1Jul 15, 2003

Memory system and method of using same

EMC CORP12 citations74
US6249878B1Jun 19, 2001

Data storage system

EMC CORP9 citations74
US5951693ASep 14, 1999

Data storage system having data reconstruction

EMC CORP9 citations74
US5850528ADec 15, 1998

Bus timing protocol for a data storage system

EMC CORP7 citations74
US7437425B2Oct 14, 2008

Data storage system having shared resource

EMC CORP8 citations73
US6988152B2Jan 17, 2006

Data storage system

EMC CORP10 citations73
US6957285B2Oct 18, 2005

Data storage system

EMC CORP6 citations73
US6138195AOct 24, 2000

Method and apparatus for hot-plugging circuit boards having low voltage logic parts into a higher voltage backplane

EMC CORP12 citations73
US5959932ASep 28, 1999

Method and apparatus for detecting errors in the writing of data to a memory

EMC CORP16 citations73
US5886930AMar 23, 1999

Bit interleaving in a memory which uses multi-bit DRAMs

EMC CORP16 citations73
US7007194B1Feb 28, 2006

Data storage system having point-to-point configuration

EMC CORP10 citations68
US6567903B1May 20, 2003

Data storage system having master/slave addressable memories

EMC CORP3 citations63
US6502149B2Dec 31, 2002

Plural bus data storage system

EMC CORP2 citations63
US5954838ASep 21, 1999

Data storage system having row/column address parity checking

EMC CORP5 citations63
US7454536B1Nov 18, 2008

Data system having a virtual queue

EMC CORP4 citations62
US6877061B2Apr 5, 2005

Data storage system having dummy printed circuit boards

EMC CORP6 citations62
US7821922B1Oct 26, 2010

Fault isolation and handling in a packet switching network

EMC CORP3 citations61
US7272668B1Sep 18, 2007

System having backplane performance capability selection logic

EMC CORP2 citations61
US6883072B2Apr 19, 2005

Memory system and method of using same

EMC CORP1 citations52

WAVE STAKE LLC

1 patent

WALTON JOHN K

1 patent