Inventor

LEE SHIH-KED

US39 patents

⚠️ This page may combine multiple inventors who share the name “LEE SHIH-KED”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LEE SHIH-KED

INTEGRATED DEVICE TECH

Cobalt silicide structure for improving gate oxide integrity and method for fabricating same

Stress-relieved shallow trench isolation (STI) structure and method for forming the same

Stress-relieved shallow trench isolation (STI) structure and method for forming the same

Method for fabricating air gap with borderless contact

Binary and ternary non-volatile CAM

Method for forming CMOS device with self-aligned contacts and region formed using salicide process

Method for forming cmos device with self-aligned contacts and region formed using salicide process

Multi-port memory cells for use in FIFO applications that support data transfers between cache and supplemental memory arrays

Methods for preventing gate oxide degradation

Semiconductor device containing a silicon-rich layer

Structures for preventing gate oxide degradation

Memory cell with reduced soft error rate

Dual-mask etch of dual-poly gate in CMOS processing

Method of forming air gaps for reducing interconnect capacitance

Self-biased electrostatic discharge protection method and circuit

Gate structures with increased etch margin for self-aligned contact and the method of forming the same

Maximization of low dielectric constant material between interconnect traces of a semiconductor circuit

Dielectric anti-reflective coating surface treatment to prevent defect generation in associated wet clean

Gate structures having sidewall spacers using selective deposition and method of forming the same

Multi-step tungsten etchback process to preserve barrier integrity in an integrated circuit structure

Method for manufacturing semiconductor device containing a silicon-rich layer

Air gap with borderless contact

Low-temperature sputtering system and method for salicide process

Method of topside and inter-metal oxide coating

Process for preventing the formation of ring defects

Die seal with reduced noise coupling

Gate structures having sidewall spacers formed using selective deposition

Maximization of low dielectric constant material between interconnect traces of a semiconductor circuit

Method of forming an oxide layer

Method for forming integrated circuit device using cell library with soft error resistant logic cells

Thin film resistor structure

Method for forming a thin film resistor structure

LAM RES CORP

Metal-containing passivation for high aspect ratio etch

Anodic aluminum oxide as hard mask for plasma etching

Atomic layer etching for subtractive metal etch

Atomic layer etching for subtractive metal etch

High etch selectivity, low stress ashable carbon hard mask

Carbon based depositions used for critical dimension control during high aspect ratio feature etches and for forming protective layers

High density, modulus, and hardness amorphous carbon films at low pressure