Inventor

KING MATTHEW J

US52 patents

⚠️ This page may combine multiple inventors who share the name “KING MATTHEW J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KING MATTHEW J

MICRON TECHNOLOGY INC

Methods of forming semiconductor structures having stair step structures

Select gate gate-induced-drain-leakage enhancement

Methods of forming a semiconductor device, and related semiconductor devices and systems

Semiconductor devices including a stair step structure, and related methods

Integrated assemblies and methods of forming integrated assemblies

Microelectronic devices including stair step structures, and related electronic devices and methods

Methods for manufacturing a memory array having strings of memory cells comprising forming bridge material between memory blocks

Memory arrays and methods used in forming a memory array comprising strings of memory cells

Gate stacks

Stair step structures including insulative materials, and related devices

Integrated circuitry, memory integrated circuitry, and methods used in forming integrated circuitry

Memory arrays and methods used in forming a memory array comprising strings of memory cells

Integrated assemblies and methods of forming integrated assemblies

Microelectronic devices including stair step structures, and related electronic devices and methods

Foundational supports within integrated assemblies

Microelectronic devices including isolation structures protruding into upper pillar portions, and related methods and systems

Forming terminations in stacked memory arrays

Select gate gate-induced-drain-leakage enhancement

Memory arrays and methods used in forming a memory array and conductive through-array-vias (TAVs)

Integrated assemblies and methods of forming integrated assemblies

Memory arrays and methods used in forming a memory array comprising strings of memory cells and operative through-array-vias

Microelectronic devices including isolation structures protruding into upper pillar portions, and related methods and systems

Foundational supports within integrated assemblies

Memory arrays and methods used in forming a memory array comprising strings of memory cells

Formation of termination structures in stacked memory arrays

Forming terminations in stacked memory arrays

Semiconductor devices and systems comprising memory cells and a source

Memory arrays and methods used in forming a memory array and conductive through-array-vias (TAVs)

Memory arrays and methods used in forming a memory array comprising strings of memory cells and operative through-array-vias

Formation of termination structures in stacked memory arrays

Microelectronic devices with source region vertically between tiered decks, and related methods and systems

Integrated assemblies having rugged material fill, and methods of forming integrated assemblies

Memory arrays and methods used in forming a memory array comprising strings of memory cells

Semiconductor devices comprising carbon-doped silicon nitride and related methods

Semiconductor device having a stack of data lines with conductive structures on both sides thereof

Semiconductor devices comprising carbon-doped silicon nitride and related methods

Microelectronic devices including conductive structures

Select gate transistor with segmented channel fin

Microelectronic devices including conductive structures, and related memory devices, electronic systems, and methods

Memory arrays and methods used in forming a memory array comprising strings of memory cells

Memory device including multiple decks of memory cells and pillars extending through the decks

Microelectronic devices including tiered stacks including conductive structures isolated by slot structures, and related electronic systems and methods

Gate stacks

Semiconductor constructions having peripheral regions with spaced apart mesas

Microelectronic devices including slot structures, and related electronic systems and methods of forming the microelectronic devices

LODESTAR LICENSING GROUP LLC

Memory array having an intervening material between adjacent memory blocks with an elongated seam therein

Microelectronic devices including pillars with partially-circular upper portions and circular lower portions, and related methods

Memory arrays and methods used in forming a memory array comprising strings of memory cells

Method for manufacturing a memory structure having stacked data lines and conductive structures on sides thereof

Memory device including multiple decks of memory cells and pillars extending through the decks