Inventor

SHU JIEHUI

US83 patents

⚠️ This page may combine multiple inventors who share the name “SHU JIEHUI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SHU JIEHUI

GLOBALFOUNDRIES INC

Vertical field effect transistor formation with critical dimension control

Gate cut structure with liner spacer and related method

Self-aligned multiple patterning processes using bi-layer mandrels and cuts formed with block masks

Transistor fins with different thickness gate dielectric

Nanowire transistors having multiple threshold voltages

Sub-fin doping method

Devices and methods of forming SADP on SRAM and SAQP on logic

Silicon liner for STI CMP stop in FinFET

Self-aligned lithographic patterning with variable spacings

Narrowed feature formation during a double patterning process

Resistor structure for integrated circuit, and related methods

Integrated circuit product with a multi-layer single diffusion break and methods of making such products

Late gate cut using selective dielectric deposition

Interconnects with variable space mandrel cuts formed by block patterning

Gate structures

Method of manufacturing finfet devices using narrow and wide gate cut openings in conjunction with a replacement metal gate process

Oxide spacer in a contact over active gate finFET and method of production thereof

Gate structures of FinFET semiconductor devices

Method for forming single diffusion breaks between finFET devices and the resulting devices

Self-aligned multiple patterning processes with layered mandrels

Methods, apparatus, and system for a semiconductor device comprising gates with short heights

Field-effect transistors with fins formed by a damascene-like process

Active gate contacts and method of fabrication thereof

Multi-step insulator formation in trenches to avoid seams in insulators

Cobalt plated via integration scheme

Methods, apparatus and system for self-aligned metal hard masks

Fin-type field effect transistor with reduced fin bulge and method

Methods of forming replacement gate structures on transistor devices

Method to improve selectivity cobalt cap process

Advanced self-aligned patterning process with sit spacer as a final dielectric etch hardmask

Semiconductor device with reduced parasitic capacitance

FinFET structure with bulbous upper insulative cap portion to protect gate height, and related method

GLOBALFOUNDRIES US INC

Forming two portion spacer after metal gate and contact formation, and related IC structure

Gate cut isolation including air gap, integrated circuit including same and related method

IC product comprising an insulating gate separation structure positioned between end surfaces of adjacent gate structures

Gate cut isolation including air gap, integrated circuit including same and related method

Semiconductor device with gate cut structure

FinFET device comprising a single diffusion break with an upper surface that is substantially coplanar with an upper surface of a fin

Gate structures

Self-aligned contact

Transistors with separately-formed source and drain

Asymmetric source drain structures

Electrical fuse formation during a multiple patterning process

Middle of line gate structures

Semiconductor devices with low resistance gate structures

IC products formed on a substrate having localized regions of high resistivity and methods of making such IC products

LDMOS integrated circuit product

Transistors with separately-formed source and drain

Semiconductor structures in a wide gate pitch region of semiconductor devices

Mask-free methods of forming structures in a semiconductor device