Inventor

HUANG HAIGOU

US65 patents

⚠️ This page may combine multiple inventors who share the name “HUANG HAIGOU”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HUANG HAIGOU

GLOBALFOUNDRIES INC

Nanosheet field-effect transistor with full dielectric isolation

Method of forming field effect transistors with replacement metal gates and contacts and resulting structure

Vertical field effect transistor formation with critical dimension control

Methods, apparatus and system for gate cut process using a stress material in a finFET device

Methods of cutting gate structures on transistor devices

Devices and methods of improving device performance through gate cut last process

Liner and cap layer for placeholder source/drain contact structure planarization and replacement

T-shaped single diffusion barrier with single mask approach process flow

Methods of forming integrated circuit structures including opening filled with insulator in metal gate

Methods of forming replacement gate structures on transistor devices

Methods, apparatus and system for providing a pre-RMG replacement metal contact for a finFET device

Vertical field-effect transistor having a dielectric spacer between a gate electrode edge and a self-aligned source/drain contact

Methods for performing a gate cut last scheme for FinFET semiconductor devices

Dielectric preservation in a replacement gate process

Vertical field effect transistor

Self-aligned deep contact for vertical FET

Method of forming field effect transistors with replacement metal gates and contacts and resulting structure

Methods, apparatus and system for replacement contact for a finFET device

Advanced structure for self-aligned contact and method for producing the same

Self-aligned lithographic patterning with variable spacings

Shallow trench isolation integration methods and devices formed thereby

Method for eliminating interlayer dielectric dishing and controlling gate height uniformity

Method of manufacturing finfet devices using narrow and wide gate cut openings in conjunction with a replacement metal gate process

Methods, apparatus, and system for a semiconductor device comprising gates with short heights

Methods of forming features on integrated circuit products

Preventing bridge formation between replacement gate and source/drain region through STI structure

Contact etch stop layer with sacrificial polysilicon layer

Method for reducing gate height variation due to overlapping masks

Methods, apparatus, and system for reducing gate cut gouging and/or gate height loss in semiconductor devices

Multi-step insulator formation in trenches to avoid seams in insulators

Methods, apparatus and system for stringer defect reduction in a trench cut region of a finFET device

Methods for forming different shapes in different regions of the same layer

Methods, apparatus, and system for reducing step height difference in semiconductor devices

Embedded silicon carbide block patterning

Structure and method for inhibiting cobalt diffusion

Shallow trench isolation integration methods and devices formed thereby

Uniform gate height for mixed-type non-planar semiconductor devices

Gap fill void and connection structures

Capping structure

Cap structure

Diffused contact extension dopants in a transistor device

Semiconductor device with reduced gate height budget

Device for improving performance through gate cut last process

Introducing self-aligned dopants in semiconductor fins

Defect-free relaxed covering layer on semiconductor substrate with lattice mismatch

Interconnects with non-mandrel cuts formed by early block patterning

GLOBALFOUNDRIES US INC

Semiconductor device with reduced gate height budget

Gap fill void and connection structures

IC product comprising a novel insulating gate separation structure for transistor devices

Multi-step insulator formation in trenches to avoid seams in insulators