Inventor
SAITO TOMOYA
US37 patents
⚠️ This page may combine multiple inventors who share the name “SAITO TOMOYA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
HALO LSI INC
21 patentsUS6670240B2Dec 30, 2003
Twin NAND device structure, array operations and fabrication method
HALO LSI INC124 citations99
US6900098B1May 31, 2005
Twin insulator charge storage device operation and its fabrication method
HALO LSI INC33 citations96
US6756271B1Jun 29, 2004
Simplified twin monos fabrication method with three extra masks to standard CMOS
HALO LSI INC64 citations96
US6707079B2Mar 16, 2004
Twin MONOS cell fabrication method and array organization
HALO LSI INC83 citations95
US7006378B1Feb 28, 2006
Array architecture and operation methods for a nonvolatile memory
HALO LSI INC31 citations93
US6825084B2Nov 30, 2004
Twin NAND device structure, array operations and fabrication method
HALO LSI INC25 citations93
US6759290B2Jul 6, 2004
Stitch and select implementation in twin MONOS array
HALO LSI INC31 citations93
US6631088B2Oct 7, 2003
Twin MONOS array metal bit organization and single cell operation
HALO LSI INC24 citations93
US7394703B2Jul 1, 2008
Twin insulator charge storage device operation and its fabrication method
HALO LSI INC12 citations84
US7170132B2Jan 30, 2007
Twin insulator charge storage device operation and its fabrication method
HALO LSI INC10 citations84
US7411247B2Aug 12, 2008
Twin insulator charge storage device operation and its fabrication method
HALO LSI INC5 citations74
US7382659B2Jun 3, 2008
Twin insulator charge storage device operation and its fabrication method
HALO LSI INC6 citations74
US7382662B2Jun 3, 2008
Twin insulator charge storage device operation and its fabrication method
HALO LSI INC4 citations74
US7359250B2Apr 15, 2008
Twin insulator charge storage device operation and its fabrication method
HALO LSI INC6 citations74
US7046556B2May 16, 2006
Twin insulator charge storage device operation and its fabrication method
HALO LSI INC4 citations74
US6838344B2Jan 4, 2005
Simplified twin monos fabrication method with three extra masks to standard CMOS
HALO LSI INC8 citations74
US7936604B2May 3, 2011
High speed operation method for twin MONOS metal bit array
HALO LSI INC4 citations63
US7391653B2Jun 24, 2008
Twin insulator charge storage device operation and its fabrication method
HALO LSI INC5 citations63
US7118961B2Oct 10, 2006
Stitch and select implementation in twin MONOS array
HALO LSI INC3 citations63
US6998658B2Feb 14, 2006
Twin NAND device structure, array operations and fabrication method
HALO LSI INC1 citations63
US7190603B2Mar 13, 2007
Nonvolatile memory array organization and usage
HALO LSI INC0 citations52
RENESAS ELECTRONICS CORP
9 patentsUS11133326B2Sep 28, 2021
Semiconductor device and method of manufacturing thereof
RENESAS ELECTRONICS CORP2 citations73
US10395742B2Aug 27, 2019
Semiconductor device
RENESAS ELECTRONICS CORP2 citations73
US10249638B2Apr 2, 2019
Semiconductor device
RENESAS ELECTRONICS CORP2 citations73
US10031792B2Jul 24, 2018
Flash memory
RENESAS ELECTRONICS CORP2 citations73
US10796768B2Oct 6, 2020
Semiconductor memory device
RENESAS ELECTRONICS CORP1 citations62
US10224083B2Mar 5, 2019
Semiconductor device, and unique ID generation method
RENESAS ELECTRONICS CORP1 citations62
US9514946B2Dec 6, 2016
Semiconductor memory incorporating insulating layers of progressively decreasing band gaps and method of manufacturing the same
RENESAS ELECTRONICS CORP2 citations60
US10559581B2Feb 11, 2020
Semiconductor device
RENESAS ELECTRONICS CORP0 citations52
US12154610B2Nov 26, 2024
Semiconductor device and semiconductor system
RENESAS ELECTRONICS CORP0 citations49