Inventor
HSU LOUIS LU-CHEN
US139 patents
Patents
50 patentsUS6632741B1Oct 14, 2003
Self-trimming method on looped patterns
IBM341 citations99
US6424011B1Jul 23, 2002
Mixed memory integration with NVRAM, dram and sram cell structures on same substrate
IBM322 citations99
US6232173B1May 15, 2001
Process for forming a memory structure that includes NVRAM, DRAM, and/or SRAM memory structures on one substrate and process for forming a new NVRAM cell structure
IBM230 citations99
US6121661ASep 19, 2000
Silicon-on-insulator structure for electrostatic discharge protection and improved heat dissipation
IBM123 citations99
US5880991AMar 9, 1999
Structure for low cost mixed memory integration, new NVRAM structure, and process for forming the mixed memory and NVRAM structure
IBM158 citations99
US5811857ASep 22, 1998
Silicon-on-insulator body-coupled gated diode for electrostatic discharge (ESD) and analog applications
IBM167 citations99
US7560784B2Jul 14, 2009
Fin PIN diode
IBM78 citations98
US7098070B2Aug 29, 2006
Device and method for fabricating double-sided SOI wafer scale package with through via connections
IBM63 citations98
US6352882B1Mar 5, 2002
Silicon-on-insulator structure for electrostatic discharge protection and improved heat dissipation
IBM80 citations98
US5729039AMar 17, 1998
SOI transistor having a self-aligned body contact
IBM100 citations97
US7489025B2Feb 10, 2009
Device and method for fabricating double-sided SOI wafer scale package with optical through via connections
IBM36 citations96
US6823293B2Nov 23, 2004
Hierarchical power supply noise monitoring device and system for very large scale integrated circuits
IBM59 citations96
US6495445B2Dec 17, 2002
Semi-sacrificial diamond for air dielectric formation
IBM47 citations96
US6177299B1Jan 23, 2001
Transistor having substantially isolated body and method of making the same
IBM55 citations96
US6141242AOct 31, 2000
Low cost mixed memory integration with substantially coplanar gate surfaces
IBM38 citations96
US6141267AOct 31, 2000
Defect management engine for semiconductor memories and memory systems
IBM68 citations96
US6107141AAug 22, 2000
Flash EEPROM
IBM83 citations96
US5910912AJun 8, 1999
Flash EEPROM with dual-sidewall gate
IBM76 citations96
US5780327AJul 14, 1998
Vertical double-gate field effect transistor
IBM68 citations96
US5689127ANov 18, 1997
Vertical double-gate field effect transistor
IBM71 citations96
US6343044B1Jan 29, 2002
Super low-power generator system for embedded applications
IBM69 citations95
US5622881AApr 22, 1997
Packing density for flash memories
IBM42 citations95
US5384152AJan 24, 1995
Method for forming capacitors with roughened single crystal plates
IBM61 citations94
US7984408B2Jul 19, 2011
Structures incorporating semiconductor device structures with reduced junction capacitance and drain induced barrier lowering
IBM36 citations93
US7893529B2Feb 22, 2011
Thermoelectric 3D cooling
IBM34 citations93
US7659168B2Feb 9, 2010
eFuse and methods of manufacturing the same
IBM24 citations93
US7531423B2May 12, 2009
Reduced-resistance finFETs by sidewall silicidation and methods of manufacturing the same
IBM23 citations93
US7439108B2Oct 21, 2008
Coplanar silicon-on-insulator (SOI) regions of different crystal orientations and methods of making the same
IBM15 citations93
US7393730B2Jul 1, 2008
Coplanar silicon-on-insulator (SOI) regions of different crystal orientations and methods of making the same
IBM17 citations93
US7384838B2Jun 10, 2008
Semiconductor FinFET structures with encapsulated gate electrodes and methods for forming such semiconductor FinFET structures
IBM39 citations93
US7305571B2Dec 4, 2007
Power network reconfiguration using MEM switches
IBM26 citations93
US6700203B1Mar 2, 2004
Semiconductor structure having in-situ formed unit resistors
IBM28 citations93
US6504173B2Jan 7, 2003
Dual gate FET and process
IBM39 citations93
US6399447B1Jun 4, 2002
Method of producing dynamic random access memory (DRAM) cell with folded bitline vertical transistor
IBM40 citations93
US6259126B1Jul 10, 2001
Low cost mixed memory integration with FERAM
IBM48 citations93
US6207530B1Mar 27, 2001
Dual gate FET and process
IBM36 citations93
US6136655AOct 24, 2000
Method of making low voltage active body semiconductor device
IBM30 citations93
US6069390AMay 30, 2000
Semiconductor integrated circuits with mesas
IBM21 citations93
US6037620AMar 14, 2000
DRAM cell with transfer device extending along perimeter of trench storage capacitor
IBM36 citations93
US5998847ADec 7, 1999
Low voltage active body semiconductor device
IBM28 citations93
US7863960B2Jan 4, 2011
Three-dimensional chip-stack synchronization
IBM38 citations92
US7736949B2Jun 15, 2010
Device and method for fabricating double-sided SOI wafer scale package with optical through via connections
IBM16 citations92
US7132821B2Nov 7, 2006
Reference current generation system
IBM16 citations92
US6603690B1Aug 5, 2003
Low-power static column redundancy scheme for semiconductor memories
IBM27 citations92
US5962895AOct 5, 1999
SOI transistor having a self-aligned body contact
IBM31 citations92
US5874764AFeb 23, 1999
Modular MOSFETS for high aspect ratio applications
IBM30 citations92
US5753525AMay 19, 1998
Method of making EEPROM cell with improved coupling ratio
IBM33 citations92
US5721485AFeb 24, 1998
High performance on-chip voltage regulator designs
IBM40 citations92
US7268624B2Sep 11, 2007
Differential amplifier offset voltage minimization independently from common mode voltage adjustment
IBM20 citations91
US6674676B1Jan 6, 2004
Column redundancy system and method for a micro-cell embedded DRAM (e-DRAM) architecture
IBM17 citations91
Showing the top 50 of 139 patents by PatentIndex Score.