Inventor

MRUGALSKI GRZEGORZ

PL39 patents

⚠️ This page may combine multiple inventors who share the name “MRUGALSKI GRZEGORZ”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MRUGALSKI GRZEGORZ

MENTOR GRAPHICS CORP

Low power scan testing techniques and apparatus

Multi-stage test response compactors

Low power decompression of test cubes

Compressing test responses using a compactor

Decompressors for low power decompression of test patterns

Test-per-clock based on dynamically-partitioned reconfigurable scan chains

Test generation for test-per-clock

Test-per-clock based on dynamically-partitioned reconfigurable scan chains

Fault-driven scan chain configuration for test-per-clock

Low power testing based on dynamic grouping of scan

Deterministic built-in self-test based on compressed test patterns stored on chip and their derivatives

Selective per-cycle masking of scan chains for system level test

Compression based on deterministic vector clustering of incompatible test cubes

Fault diagnosis of compressed test responses

Scan chain stitching for test-per-clock

Multi-stage test response compactors

Selective per-cycle masking of scan chains for system level test

Scan chain configuration for test-per-clock based on circuit topology

RAJSKI JANUSZ

Multi-stage test response compactors

Low power decompression of test cubes

Compressing test responses using a compactor

Decompressors for low power decompression of test patterns

Selective per-cycle masking of scan chains for system level test

Compressing test responses using a compactor

Fault diagnosis of compressed test responses

Fault diagnosis of compressed test responses having one or more unknown states

Adaptive fault diagnosis of compressed test responses

Selective per-cycle masking of scan chains for system level test

Decompressors for low power decompression of test patterns

Test scheduling with pattern-independent test access mechanism

Test generator for low power built-in self-test

SIEMENS IND SOFTWARE INC

Trajectory-optimized test pattern generation for built-in self-test

Suspect resolution for scan chain defect diagnosis

X-masking for in-system deterministic test

Universal compactor architecture for testing circuits

CHENG WU-TUNG

Accurately identifying failing scan bits in compression environments

LIN XIJIANG

Low power scan testing techniques and apparatus

CZYSZ DARIUSZ

Low power compression of incompatible test cubes

KASSAB MARK

Test scheduling and test access in test compression environment