Inventor

MUKHERJEE NILANJAN

US92 patents

⚠️ This page may combine multiple inventors who share the name “MUKHERJEE NILANJAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MUKHERJEE NILANJAN

RAJSKI JANUSZ

Test pattern compression for an integrated circuit test environment

Decompressor/PRPG for applying pseudo-random and deterministic test patterns

Method and apparatus for selectively compacting test responses

Test pattern compression for an integrated circuit test environment

Decompressor/PRPG for applying pseudo-random and deterministic test patterns

Continuous application and decompression of test patterns to a circuit-under-test

Method for synthesizing linear finite state machines

Selective per-cycle masking of scan chains for system level test

Scan test application through high-speed serial input/outputs

Selective per-cycle masking of scan chains for system level test

Method and apparatus for selectively compacting test responses

At-speed scan testing with controlled switching activity

(unassigned)

Method and apparatus for selectively compacting test responses

Decompressor/PRPG for applying pseudo-random and deterministic test patterns

Method and apparatus for selectively compacting test responses

Test pattern compression for an integrated circuit test environment

Method for synthesizing linear finite state machines

Test pattern compression for an integrated circuit test environment

Method for synthesizing linear finite state machines

Method for synthesizing linear finite state machines

Scheduling the concurrent testing of multiple cores embedded in an integrated circuit

MENTOR GRAPHICS CORP

On-chip comparison and response collection tools and techniques

Test pattern compression for an integrated circuit test environment

Continuous application and decompression of test patterns to a circuit-under-test

Decompressor/PRPG for applying pseudo-random and deterministic test patterns

Method and apparatus for selectively compacting test responses

On-chip comparison and response collection tools and techniques

On-chip comparison and response collection tools and techniques

Method for synthesizing linear finite state machines

MUKHERJEE NILANJAN

Reduced-pin-count-testing architectures for applying test patterns

On-chip comparison and response collection tools and techniques

Flexible memory built-in-self-test (MBIST) method and apparatus

Programmable memory built-in-self-test (MBIST) method and apparatus

Performing memory built-in-self-test (MBIST)

Testing memories using algorithm selection

System, method, and computer program product for smoothing

IBM

Switch routing table utilizing software defined network (SDN) controller programmed route segregation and prioritization

Layer 2 packet switching without look-up table for ethernet switches

Switch routing table utilizing software defined network (SDN) controller programmed route segregation and prioritization

Support for converged traffic over ethernet link aggregation (LAG)

LENOVO ENTPR SOLUTIONS SINGAPORE PTE LTD

Scalable network overlay virtualization using conventional virtual switches

Quality of service in multi-tenant network

ANANTHARAM SUSHMA

Communication transport protocol for distributed information technology architectures

Layer 2 packet switching without look-up table for ethernet switches

LUCENT TECHNOLOGIES INC

Bist architecture for detecting path-delay faults in a sequential circuit

KAMBLE KESHAV

Data traffic handling in a distributed fabric protocol (DFP) switching network architecture

AGERE SYST GUARDIAN CORP

Method for self-testing integrated circuits

RAJSKI JANSUZ

Continuous application and decompression of test patterns to a circuit-under-test

BISWAS AMITABHA

Virtual network overlays

KAMBLE KESHAV G

Scalable virtual appliance cloud (SVAC) and devices usable in an SVAC