Inventor

WU KUO-MING

TW122 patents

⚠️ This page may combine multiple inventors who share the name “WU KUO-MING”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WU KUO-MING

TAIWAN SEMICONDUCTOR MFG CO LTD

3DIC structure and methods of forming

Multi-wafer capping layer for metal arcing protection

Trim wall protection method for multi-wafer stacking

Bonding support structure (and related process) for wafer stacking

Techniques for wafer stack processing

Hybrid bonding technology for stacking integrated circuits

High dielectric constant structure for the vertical transfer gates of a complementary metal-oxide semiconductor (CMOS) image sensor

High voltage metal-oxide-semiconductor (HVMOS) device integrated with a high voltage junction termination (HVJT) device

Semiconductor structure and associated fabricating method

Hybrid bonding technology for stacking integrated circuits

Trim wall protection method for multi-wafer stacking

Method for forming hybrid-bonding structure

Hybrid bonding technology for stacking integrated circuits

Hybrid bonding technology for stacking integrated circuits

Seal ring structures and methods of forming same

Magnetoresistive random access memory cell and fabricating the same

Semiconductor device and integrated inductor

High voltage transistor structure

Semiconductor structure and associated fabricating method

High voltage metal-oxide-semiconductor (HVMOS) device integrated with a high voltage junction termination (HVJT) device

High voltage transistor structure

Semiconductor structure and associated fabricating method

3DIC structure and methods of forming

Semiconductor structure and associated fabricating method

High voltage transistor structure and method

Semiconductor device

Semiconductor device structure having a gate structure and overlying dielectric layer

Semiconductor device including a capacitor

Self-aligned contact for trench MOSFET

Multi-wafer capping layer for metal arcing protection

Trim wall protection method for multi-wafer stacking

Multi-wafer capping layer for metal arcing protection

Semiconductor structure and manufacturing method thereof

Bonding support structure (and related process) for wafer stacking

TAIWAN SEMICONDUCTOR MFG

Method of forming high voltage devices with retrograde well

High voltage semiconductor devices and methods for fabricating the same

High voltage lateral diffused MOSFET device

High voltage semiconductor devices and methods for fabricating the same

Fully isolated high-voltage MOS device

MEDIATEK INC

Method and apparatus for I/Q mismatch calibration of transmitter

Method and apparatus for I/Q mismatch calibration in a receiver

Branch metric computation and add-compare-select operation in viterbi decoders

Avoidance mechanism for co-channel interference in a network

EISAI R&D MAN CO LTD

Compounds for preparing immunological adjuvant

REALTEK SEMICONDUCTOR CORP

Band averaging circuit and related method for carrier frequency offset estimation in a multi-band multi-carrier communication system

WEI CHI-SAN

Fully isolated high-voltage MOS device

WU KUO-MING

Magnetoresistive random access memory cell and fabricating the same

ALLELIX PHARM ECO L P

Slow-onset, long-lasting dopamine reuptake blockers

FANG FRANCIS G

Compounds for preparing immunological adjuvant

CHEN CHIH-MING

Technique for smoothing an interface between layers of a semiconductor device