Inventor

OSTERMAYR MARTIN

US32 patents

⚠️ This page may combine multiple inventors who share the name “OSTERMAYR MARTIN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

OSTERMAYR MARTIN

INFINEON TECHNOLOGIES AG

Semiconductor device and method for manufacturing the same

Memory cell, memory device, device and method of accessing a memory cell

Multi-transistor memory cells

Gridded contacts in semiconductor devices

Semiconductor memory cell and associated fabrication method

Programmable mask ROM building element and process of manufacture

Method of operating a memory cell, memory cell and memory unit

ROM memory cell having defined bit line voltages

Homogenous cell array

Method for programming a memory arrangement and programmed memory arrangement

Semiconductor memory cell and corresponding method of producing same

Method for preventing the formation of dentrites in a semiconductor

Bit line dummy core-cell and method for producing a bit line dummy core-cell

Capacitors and methods of manufacture thereof

Memory cell, read device for memory cell, memory assembly, and corresponding method

Semiconductor read-only memory configuration with substrate contacts and polysilicon bridge cells

INTEL CORP

Semiconductor dies and devices with frontside and backside coils for inductive coupling

Threshold voltage tuning for nanoribbon-based transistors

Semiconductor dies and devices with a coil for inductive coupling

Semiconductor structure and method for forming a semiconductor structure

Semiconductor devices and methods for forming a semiconductor device

Buried power rails integrated with decoupling capacitance

OSTERMAYR MARTIN

Semiconductor memory device and method

Transistor level routing

Capacitors and methods of manufacture thereof

Transistor level routing

INTEL IP CORP

Memory circuit and method for operating a first MRAM and a second MRAM set of memory cells configured to operate in a direct access mode and/or refresh mode

Memory circuit and method for operating a first and a second set of memory cells in direct memory access mode with refresh

KOEPPE SIEGMAR

Method and device for controlling a memory access and correspondingly configured semiconductor memory

HAFFNER HENNING

L-shaped feature, method of making an L-shaped feature and method of making an L-shaped structure

SCHROEDER UWE PAUL

SRAM memory cell having a dogleg shaped gate electrode structure

SCHIWON ROBERTO

Methods for forming contacts in semiconductor devices